0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Faraday Technology FTPCI100 PCI Host Bridge
0008
0009 maintainers:
0010 - Linus Walleij <linus.walleij@linaro.org>
0011
0012 description: |
0013 This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
0014 is a generic IP block from Faraday Technology. It exists in two variants:
0015 plain and dual PCI. The plain version embeds a cascading interrupt controller
0016 into the host bridge. The dual version routes the interrupts to the host
0017 chips interrupt controller.
0018 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
0019 Technology) and product ID 0x4321.
0020 I/O space considerations:
0021 The plain variant has 128MiB of non-prefetchable memory space, whereas the
0022 "dual" variant has 64MiB. Take this into account when describing the ranges.
0023
0024 Interrupt map considerations:
0025
0026 The "dual" variant will get INT A, B, C, D from the system interrupt controller
0027 and should point to respective interrupt in that controller in its interrupt-map.
0028
0029 The code which is the only documentation of how the Faraday PCI (the non-dual
0030 variant) interrupts assigns the default interrupt mapping/swizzling has
0031 typically been like this, doing the swizzling on the interrupt controller side
0032 rather than in the interconnect:
0033
0034 interrupt-map-mask = <0xf800 0 0 7>;
0035 interrupt-map =
0036 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
0037 <0x4800 0 0 2 &pci_intc 1>,
0038 <0x4800 0 0 3 &pci_intc 2>,
0039 <0x4800 0 0 4 &pci_intc 3>,
0040 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
0041 <0x5000 0 0 2 &pci_intc 2>,
0042 <0x5000 0 0 3 &pci_intc 3>,
0043 <0x5000 0 0 4 &pci_intc 0>,
0044 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
0045 <0x5800 0 0 2 &pci_intc 3>,
0046 <0x5800 0 0 3 &pci_intc 0>,
0047 <0x5800 0 0 4 &pci_intc 1>,
0048 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
0049 <0x6000 0 0 2 &pci_intc 0>,
0050 <0x6000 0 0 3 &pci_intc 1>,
0051 <0x6000 0 0 4 &pci_intc 2>;
0052
0053 allOf:
0054 - $ref: /schemas/pci/pci-bus.yaml#
0055
0056 properties:
0057 compatible:
0058 oneOf:
0059 - items:
0060 - const: cortina,gemini-pci
0061 - const: faraday,ftpci100
0062 - items:
0063 - const: cortina,gemini-pci-dual
0064 - const: faraday,ftpci100-dual
0065 - const: faraday,ftpci100
0066 - const: faraday,ftpci100-dual
0067
0068 reg:
0069 maxItems: 1
0070
0071 "#address-cells":
0072 const: 3
0073
0074 "#interrupt-cells":
0075 const: 1
0076
0077 ranges:
0078 minItems: 2
0079
0080 dma-ranges:
0081 minItems: 3
0082 description: |
0083 three ranges for the inbound memory region. The ranges must
0084 be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
0085 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
0086 pre-fetchable.
0087
0088 clocks:
0089 items:
0090 - description: peripheral clock (PCLK)
0091 - description: PCI clock (PCICLK).
0092 description: |
0093 If these are not present, they are assumed to be
0094 hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
0095
0096 clock-names:
0097 items:
0098 - const: PCLK
0099 - const: PCICLK
0100
0101 interrupt-controller:
0102 type: object
0103
0104 required:
0105 - reg
0106 - compatible
0107 - "#interrupt-cells"
0108 - interrupt-map-mask
0109 - interrupt-map
0110 - dma-ranges
0111
0112 if:
0113 properties:
0114 compatible:
0115 contains:
0116 const: faraday,ftpci100
0117 then:
0118 required:
0119 - interrupt-controller
0120
0121 unevaluatedProperties: false
0122
0123 examples:
0124 - |
0125 #include <dt-bindings/interrupt-controller/irq.h>
0126 pci@50000000 {
0127 compatible = "cortina,gemini-pci", "faraday,ftpci100";
0128 reg = <0x50000000 0x100>;
0129 device_type = "pci";
0130 #address-cells = <3>;
0131 #size-cells = <2>;
0132 #interrupt-cells = <1>;
0133
0134 bus-range = <0x00 0xff>;
0135 ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
0136 <0x01000000 0 0 0x50000000 0 0x00100000>,
0137 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
0138 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
0139
0140 /* DMA ranges */
0141 dma-ranges =
0142 /* 128MiB at 0x00000000-0x07ffffff */
0143 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
0144 /* 64MiB at 0x00000000-0x03ffffff */
0145 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
0146 /* 64MiB at 0x00000000-0x03ffffff */
0147 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
0148
0149 interrupt-map-mask = <0xf800 0 0 7>;
0150 interrupt-map =
0151 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
0152 <0x4800 0 0 2 &pci_intc 1>,
0153 <0x4800 0 0 3 &pci_intc 2>,
0154 <0x4800 0 0 4 &pci_intc 3>,
0155 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
0156 <0x5000 0 0 2 &pci_intc 2>,
0157 <0x5000 0 0 3 &pci_intc 3>,
0158 <0x5000 0 0 4 &pci_intc 0>,
0159 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
0160 <0x5800 0 0 2 &pci_intc 3>,
0161 <0x5800 0 0 3 &pci_intc 0>,
0162 <0x5800 0 0 4 &pci_intc 1>,
0163 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
0164 <0x6000 0 0 2 &pci_intc 0>,
0165 <0x6000 0 0 3 &pci_intc 0>,
0166 <0x6000 0 0 4 &pci_intc 0>;
0167 pci_intc: interrupt-controller {
0168 interrupt-parent = <&intcon>;
0169 interrupt-controller;
0170 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0171 #address-cells = <0>;
0172 #interrupt-cells = <1>;
0173 };
0174 };
