bindings/pci/brcm%2Ciproc-pcie.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom iProc PCIe controller with the platform bus interface
0008
0009 maintainers:
0010   - Ray Jui <ray.jui@broadcom.com>
0011   - Scott Branden <scott.branden@broadcom.com>
0012
0013 allOf:
0014   - $ref: /schemas/pci/pci-bus.yaml#
0015   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
0016
0017 properties:
0018   compatible:
0019     items:
0020       - enum:
0021           # for the first generation of PAXB based controller, used in SoCs
0022           # including NSP, Cygnus, NS2, and Pegasus
0023           - brcm,iproc-pcie
0024           # for the second generation of PAXB-based controllers, used in
0025           # Stingray
0026           - brcm,iproc-pcie-paxb-v2
0027           # For the first generation of PAXC based controller, used in NS2
0028           - brcm,iproc-pcie-paxc
0029           # For the second generation of PAXC based controller, used in Stingray
0030           - brcm,iproc-pcie-paxc-v2
0031
0032   reg:
0033     maxItems: 1
0034     description: >
0035        Base address and length of the PCIe controller I/O register space
0036
0037   interrupt-map: true
0038
0039   interrupt-map-mask: true
0040
0041   "#interrupt-cells":
0042     const: 1
0043
0044   ranges:
0045     minItems: 1
0046     maxItems: 2
0047     description: >
0048       Ranges for the PCI memory and I/O regions
0049
0050   phys:
0051     maxItems: 1
0052
0053   phy-names:
0054     items:
0055       - const: pcie-phy
0056
0057   bus-range: true
0058
0059   dma-coherent: true
0060
0061   "#address-cells": true
0062
0063   "#size-cells": true
0064
0065   device_type: true
0066
0067   brcm,pcie-ob:
0068     type: boolean
0069     description: >
0070       Some iProc SoCs do not have the outbound address mapping done by the
0071       ASIC after power on reset. In this case, SW needs to configure it
0072
0073   brcm,pcie-ob-axi-offset:
0074     $ref: /schemas/types.yaml#/definitions/uint32
0075     description: >
0076        The offset from the AXI address to the internal address used by the
0077        iProc PCIe core (not the PCIe address)
0078
0079   msi:
0080     type: object
0081     properties:
0082       compatible:
0083         items:
0084           - const: brcm,iproc-msi
0085
0086   msi-parent: true
0087
0088   msi-controller: true
0089
0090   brcm,pcie-msi-inten:
0091     type: boolean
0092     description: >
0093       Needs to be present for some older iProc platforms that require the
0094       interrupt enable registers to be set explicitly to enable MSI
0095
0096 dependencies:
0097   brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
0098   brcm,pcie-msi-inten: [msi-controller]
0099
0100 required:
0101   - compatible
0102   - reg
0103   - ranges
0104
0105 if:
0106   properties:
0107     compatible:
0108       contains:
0109         enum:
0110           - brcm,iproc-pcie
0111 then:
0112   required:
0113     - interrupt-map
0114     - interrupt-map-mask
0115
0116 unevaluatedProperties: false
0117
0118 examples:
0119   - |
0120    #include <dt-bindings/interrupt-controller/arm-gic.h>
0121
0122    bus {
0123       #address-cells = <1>;
0124       #size-cells = <1>;
0125            pcie0: pcie@18012000 {
0126               compatible = "brcm,iproc-pcie";
0127               reg = <0x18012000 0x1000>;
0128
0129               #interrupt-cells = <1>;
0130               interrupt-map-mask = <0 0 0 0>;
0131               interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
0132
0133               linux,pci-domain = <0>;
0134
0135               bus-range = <0x00 0xff>;
0136
0137               #address-cells = <3>;
0138               #size-cells = <2>;
0139               device_type = "pci";
0140               ranges = <0x81000000 0 0     0x28000000 0 0x00010000>,
0141                    <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
0142
0143               phys = <&phy 0 5>;
0144               phy-names = "pcie-phy";
0145
0146               brcm,pcie-ob;
0147               brcm,pcie-ob-axi-offset = <0x00000000>;
0148
0149               msi-parent = <&msi0>;
0150
0151               /* iProc event queue based MSI */
0152               msi0: msi {
0153                  compatible = "brcm,iproc-msi";
0154                  msi-controller;
0155                  interrupt-parent = <&gic>;
0156                  interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
0157                          <GIC_SPI 97 IRQ_TYPE_NONE>,
0158                          <GIC_SPI 98 IRQ_TYPE_NONE>,
0159                          <GIC_SPI 99 IRQ_TYPE_NONE>;
0160               };
0161            };
0162
0163            pcie1: pcie@18013000 {
0164               compatible = "brcm,iproc-pcie";
0165               reg = <0x18013000 0x1000>;
0166
0167               #interrupt-cells = <1>;
0168               interrupt-map-mask = <0 0 0 0>;
0169               interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
0170
0171               linux,pci-domain = <1>;
0172
0173               bus-range = <0x00 0xff>;
0174
0175               #address-cells = <3>;
0176               #size-cells = <2>;
0177               device_type = "pci";
0178               ranges = <0x81000000 0 0     0x48000000 0 0x00010000>,
0179                    <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
0180
0181               phys = <&phy 1 6>;
0182               phy-names = "pcie-phy";
0183            };
0184     };