Back to home page

OSCL-LXR

 
 

    


0001 * Axis ARTPEC-6 PCIe interface
0002 
0003 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
0004 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
0005 
0006 Required properties:
0007 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
0008               "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
0009               "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
0010               "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
0011 - reg: base addresses and lengths of the PCIe controller (DBI),
0012         the PHY controller, and configuration address space.
0013 - reg-names: Must include the following entries:
0014         - "dbi"
0015         - "phy"
0016         - "config"
0017 - interrupts: A list of interrupt outputs of the controller. Must contain an
0018   entry for each entry in the interrupt-names property.
0019 - interrupt-names: Must include the following entries:
0020         - "msi": The interrupt that is asserted when an MSI is received
0021 - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
0022         used to enable and control the Synopsys IP.
0023 
0024 Example:
0025 
0026         pcie@f8050000 {
0027                 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
0028                 reg = <0xf8050000 0x2000
0029                        0xf8040000 0x1000
0030                        0xc0000000 0x2000>;
0031                 reg-names = "dbi", "phy", "config";
0032                 #address-cells = <3>;
0033                 #size-cells = <2>;
0034                 device_type = "pci";
0035                           /* downstream I/O */
0036                 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
0037                           /* non-prefetchable memory */
0038                           0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
0039                 num-lanes = <2>;
0040                 bus-range = <0x00 0xff>;
0041                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0042                 interrupt-names = "msi";
0043                 #interrupt-cells = <1>;
0044                 interrupt-map-mask = <0 0 0 0x7>;
0045                 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
0046                                 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0047                                 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0048                                 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0049                 axis,syscon-pcie = <&syscon>;
0050         };