bindings/pci/apple%2Cpcie.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Apple PCIe host controller
0008
0009 maintainers:
0010   - Mark Kettenis <kettenis@openbsd.org>
0011
0012 description: |
0013   The Apple PCIe host controller is a PCIe host controller with
0014   multiple root ports present in Apple ARM SoC platforms, including
0015   various iPhone and iPad devices and the "Apple Silicon" Macs.
0016   The controller incorporates Synopsys DesigWare PCIe logic to
0017   implements its root ports.  But the ATU found on most DesignWare
0018   PCIe host bridges is absent.
0019
0020   All root ports share a single ECAM space, but separate GPIOs are
0021   used to take the PCI devices on those ports out of reset.  Therefore
0022   the standard "reset-gpios" and "max-link-speed" properties appear on
0023   the child nodes that represent the PCI bridges that correspond to
0024   the individual root ports.
0025
0026   MSIs are handled by the PCIe controller and translated into regular
0027   interrupts.  A range of 32 MSIs is provided.  These 32 MSIs can be
0028   distributed over the root ports as the OS sees fit by programming
0029   the PCIe controller's port registers.
0030
0031 properties:
0032   compatible:
0033     items:
0034       - enum:
0035           - apple,t8103-pcie
0036           - apple,t6000-pcie
0037       - const: apple,pcie
0038
0039   reg:
0040     minItems: 3
0041     maxItems: 6
0042
0043   reg-names:
0044     minItems: 3
0045     items:
0046       - const: config
0047       - const: rc
0048       - const: port0
0049       - const: port1
0050       - const: port2
0051       - const: port3
0052
0053   ranges:
0054     minItems: 2
0055     maxItems: 2
0056
0057   interrupts:
0058     description:
0059       Interrupt specifiers, one for each root port.
0060     minItems: 1
0061     maxItems: 4
0062
0063   msi-parent: true
0064
0065   msi-ranges:
0066     maxItems: 1
0067
0068   iommu-map: true
0069   iommu-map-mask: true
0070
0071   power-domains:
0072     maxItems: 1
0073
0074 required:
0075   - compatible
0076   - reg
0077   - reg-names
0078   - bus-range
0079   - interrupts
0080   - msi-controller
0081   - msi-parent
0082   - msi-ranges
0083
0084 unevaluatedProperties: false
0085
0086 allOf:
0087   - $ref: /schemas/pci/pci-bus.yaml#
0088   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
0089   - if:
0090       properties:
0091         compatible:
0092           contains:
0093             const: apple,t8103-pcie
0094     then:
0095       properties:
0096         reg:
0097           maxItems: 5
0098         interrupts:
0099           maxItems: 3
0100
0101 examples:
0102   - |
0103     #include <dt-bindings/interrupt-controller/apple-aic.h>
0104
0105     soc {
0106       #address-cells = <2>;
0107       #size-cells = <2>;
0108
0109       pcie0: pcie@690000000 {
0110         compatible = "apple,t8103-pcie", "apple,pcie";
0111         device_type = "pci";
0112
0113         reg = <0x6 0x90000000 0x0 0x1000000>,
0114               <0x6 0x80000000 0x0 0x100000>,
0115               <0x6 0x81000000 0x0 0x4000>,
0116               <0x6 0x82000000 0x0 0x4000>,
0117               <0x6 0x83000000 0x0 0x4000>;
0118         reg-names = "config", "rc", "port0", "port1", "port2";
0119
0120         interrupt-parent = <&aic>;
0121         interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
0122                      <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
0123                      <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
0124
0125         msi-controller;
0126         msi-parent = <&pcie0>;
0127         msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
0128
0129         iommu-map = <0x100 &dart0 1 1>,
0130                     <0x200 &dart1 1 1>,
0131                     <0x300 &dart2 1 1>;
0132         iommu-map-mask = <0xff00>;
0133
0134         bus-range = <0 3>;
0135         #address-cells = <3>;
0136         #size-cells = <2>;
0137         ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
0138                  <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
0139
0140         power-domains = <&ps_apcie_gp>;
0141         pinctrl-0 = <&pcie_pins>;
0142         pinctrl-names = "default";
0143
0144         pci@0,0 {
0145           device_type = "pci";
0146           reg = <0x0 0x0 0x0 0x0 0x0>;
0147           reset-gpios = <&pinctrl_ap 152 0>;
0148
0149           #address-cells = <3>;
0150           #size-cells = <2>;
0151           ranges;
0152         };
0153
0154         pci@1,0 {
0155           device_type = "pci";
0156           reg = <0x800 0x0 0x0 0x0 0x0>;
0157           reset-gpios = <&pinctrl_ap 153 0>;
0158
0159           #address-cells = <3>;
0160           #size-cells = <2>;
0161           ranges;
0162         };
0163
0164         pci@2,0 {
0165           device_type = "pci";
0166           reg = <0x1000 0x0 0x0 0x0 0x0>;
0167           reset-gpios = <&pinctrl_ap 33 0>;
0168
0169           #address-cells = <3>;
0170           #size-cells = <2>;
0171           ranges;
0172         };
0173       };
0174     };