0001 Amlogic Meson AXG DWC PCIE SoC controller
0002
0003 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
0004 It shares common functions with the PCIe DesignWare core driver and
0005 inherits common properties defined in
0006 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
0007
0008 Additional properties are described here:
0009
0010 Required properties:
0011 - compatible:
0012 should contain :
0013 - "amlogic,axg-pcie" for AXG SoC Family
0014 - "amlogic,g12a-pcie" for G12A SoC Family
0015 to identify the core.
0016 - reg:
0017 should contain the configuration address space.
0018 - reg-names: Must be
0019 - "elbi" External local bus interface registers
0020 - "cfg" Meson specific registers
0021 - "config" PCIe configuration space
0022 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
0023 - clocks: Must contain an entry for each entry in clock-names.
0024 - clock-names: Must include the following entries:
0025 - "pclk" PCIe GEN 100M PLL clock
0026 - "port" PCIe_x(A or B) RC clock gate
0027 - "general" PCIe Phy clock
0028 - resets: phandle to the reset lines.
0029 - reset-names: must contain "port" and "apb"
0030 - "port" Port A or B reset
0031 - "apb" Share APB reset
0032 - phys: should contain a phandle to the PCIE phy
0033 - phy-names: must contain "pcie"
0034
0035 - device_type:
0036 should be "pci". As specified in snps,dw-pcie.yaml
0037
0038
0039 Example configuration:
0040
0041 pcie: pcie@f9800000 {
0042 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
0043 reg = <0x0 0xf9800000 0x0 0x400000
0044 0x0 0xff646000 0x0 0x2000
0045 0x0 0xf9f00000 0x0 0x100000>;
0046 reg-names = "elbi", "cfg", "config";
0047 reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
0048 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
0049 #interrupt-cells = <1>;
0050 interrupt-map-mask = <0 0 0 0>;
0051 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
0052 bus-range = <0x0 0xff>;
0053 #address-cells = <3>;
0054 #size-cells = <2>;
0055 device_type = "pci";
0056 ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
0057
0058 clocks = <&clkc CLKID_USB
0059 &clkc CLKID_PCIE_A
0060 &clkc CLKID_PCIE_CML_EN0>;
0061 clock-names = "general",
0062 "pclk",
0063 "port";
0064 resets = <&reset RESET_PCIE_A>,
0065 <&reset RESET_PCIE_APB>;
0066 reset-names = "port",
0067 "apb";
0068 phys = <&pcie_phy>;
0069 phy-names = "pcie";
0070 };
