0001 * Altera PCIe controller
0002
0003 Required properties:
0004 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
0005 - reg: a list of physical base address and length for TXS and CRA.
0006 For "altr,pcie-root-port-2.0", additional HIP base address and length.
0007 - reg-names: must include the following entries:
0008 "Txs": TX slave port region
0009 "Cra": Control register access region
0010 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
0011 - interrupts: specifies the interrupt source of the parent interrupt
0012 controller. The format of the interrupt specifier depends
0013 on the parent interrupt controller.
0014 - device_type: must be "pci"
0015 - #address-cells: set to <3>
0016 - #size-cells: set to <2>
0017 - #interrupt-cells: set to <1>
0018 - ranges: describes the translation of addresses for root ports and
0019 standard PCI regions.
0020 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
0021 mapping of the PCIe interface to interrupt numbers.
0022
0023 Optional properties:
0024 - msi-parent: Link to the hardware entity that serves as the MSI controller
0025 for this PCIe controller.
0026 - bus-range: PCI bus numbers covered
0027
0028 Example
0029 pcie_0: pcie@c00000000 {
0030 compatible = "altr,pcie-root-port-1.0";
0031 reg = <0xc0000000 0x20000000>,
0032 <0xff220000 0x00004000>;
0033 reg-names = "Txs", "Cra";
0034 interrupt-parent = <&hps_0_arm_gic_0>;
0035 interrupts = <0 40 4>;
0036 interrupt-controller;
0037 #interrupt-cells = <1>;
0038 bus-range = <0x0 0xFF>;
0039 device_type = "pci";
0040 msi-parent = <&msi_to_gic_gen_0>;
0041 #address-cells = <3>;
0042 #size-cells = <2>;
0043 interrupt-map-mask = <0 0 0 7>;
0044 interrupt-map = <0 0 0 1 &pcie_0 1>,
0045 <0 0 0 2 &pcie_0 2>,
0046 <0 0 0 3 &pcie_0 3>,
0047 <0 0 0 4 &pcie_0 4>;
0048 ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
0049 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
0050 };
