0001 Aardvark PCIe controller
0002
0003 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
0004
0005 The Device Tree node describing an Aardvark PCIe controller must
0006 contain the following properties:
0007
0008 - compatible: Should be "marvell,armada-3700-pcie"
0009 - reg: range of registers for the PCIe controller
0010 - interrupts: the interrupt line of the PCIe controller
0011 - #address-cells: set to <3>
0012 - #size-cells: set to <2>
0013 - device_type: set to "pci"
0014 - ranges: ranges for the PCI memory and I/O regions
0015 - #interrupt-cells: set to <1>
0016 - msi-controller: indicates that the PCIe controller can itself
0017 handle MSI interrupts
0018 - msi-parent: pointer to the MSI controller to be used
0019 - interrupt-map-mask and interrupt-map: standard PCI properties to
0020 define the mapping of the PCIe interface to interrupt numbers.
0021 - bus-range: PCI bus numbers covered
0022 - phys: the PCIe PHY handle
0023 - max-link-speed: see pci.txt
0024 - reset-gpios: see pci.txt
0025
0026 In addition, the Device Tree describing an Aardvark PCIe controller
0027 must include a sub-node that describes the legacy interrupt controller
0028 built into the PCIe controller. This sub-node must have the following
0029 properties:
0030
0031 - interrupt-controller
0032 - #interrupt-cells: set to <1>
0033
0034 Example:
0035
0036 pcie0: pcie@d0070000 {
0037 compatible = "marvell,armada-3700-pcie";
0038 device_type = "pci";
0039 reg = <0 0xd0070000 0 0x20000>;
0040 #address-cells = <3>;
0041 #size-cells = <2>;
0042 bus-range = <0x00 0xff>;
0043 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0044 #interrupt-cells = <1>;
0045 msi-controller;
0046 msi-parent = <&pcie0>;
0047 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
0048 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
0049 interrupt-map-mask = <0 0 0 7>;
0050 interrupt-map = <0 0 0 1 &pcie_intc 0>,
0051 <0 0 0 2 &pcie_intc 1>,
0052 <0 0 0 3 &pcie_intc 2>,
0053 <0 0 0 4 &pcie_intc 3>;
0054 phys = <&comphy1 0>;
0055 pcie_intc: interrupt-controller {
0056 interrupt-controller;
0057 #interrupt-cells = <1>;
0058 };
0059 };
