0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Generic OPP (Operating Performance Points) Bindings
0008
0009 maintainers:
0010 - Viresh Kumar <viresh.kumar@linaro.org>
0011
0012 allOf:
0013 - $ref: opp-v2-base.yaml#
0014
0015 properties:
0016 compatible:
0017 const: operating-points-v2
0018
0019 unevaluatedProperties: false
0020
0021 examples:
0022 - |
0023 /*
0024 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
0025 * together.
0026 */
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 cpu@0 {
0032 compatible = "arm,cortex-a9";
0033 device_type = "cpu";
0034 reg = <0>;
0035 next-level-cache = <&L2>;
0036 clocks = <&clk_controller 0>;
0037 clock-names = "cpu";
0038 cpu-supply = <&cpu_supply0>;
0039 operating-points-v2 = <&cpu0_opp_table0>;
0040 };
0041
0042 cpu@1 {
0043 compatible = "arm,cortex-a9";
0044 device_type = "cpu";
0045 reg = <1>;
0046 next-level-cache = <&L2>;
0047 clocks = <&clk_controller 0>;
0048 clock-names = "cpu";
0049 cpu-supply = <&cpu_supply0>;
0050 operating-points-v2 = <&cpu0_opp_table0>;
0051 };
0052 };
0053
0054 cpu0_opp_table0: opp-table {
0055 compatible = "operating-points-v2";
0056 opp-shared;
0057
0058 opp-1000000000 {
0059 opp-hz = /bits/ 64 <1000000000>;
0060 opp-microvolt = <975000 970000 985000>;
0061 opp-microamp = <70000>;
0062 clock-latency-ns = <300000>;
0063 opp-suspend;
0064 };
0065 opp-1100000000 {
0066 opp-hz = /bits/ 64 <1100000000>;
0067 opp-microvolt = <1000000 980000 1010000>;
0068 opp-microamp = <80000>;
0069 clock-latency-ns = <310000>;
0070 };
0071 opp-1200000000 {
0072 opp-hz = /bits/ 64 <1200000000>;
0073 opp-microvolt = <1025000>;
0074 clock-latency-ns = <290000>;
0075 turbo-mode;
0076 };
0077 };
0078
0079 - |
0080 /*
0081 * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
0082 * independently.
0083 */
0084 cpus {
0085 #address-cells = <1>;
0086 #size-cells = <0>;
0087
0088 cpu@0 {
0089 compatible = "qcom,krait";
0090 device_type = "cpu";
0091 reg = <0>;
0092 next-level-cache = <&L2>;
0093 clocks = <&clk_controller 0>;
0094 clock-names = "cpu";
0095 cpu-supply = <&cpu_supply0>;
0096 operating-points-v2 = <&cpu_opp_table>;
0097 };
0098
0099 cpu@1 {
0100 compatible = "qcom,krait";
0101 device_type = "cpu";
0102 reg = <1>;
0103 next-level-cache = <&L2>;
0104 clocks = <&clk_controller 1>;
0105 clock-names = "cpu";
0106 cpu-supply = <&cpu_supply1>;
0107 operating-points-v2 = <&cpu_opp_table>;
0108 };
0109
0110 cpu@2 {
0111 compatible = "qcom,krait";
0112 device_type = "cpu";
0113 reg = <2>;
0114 next-level-cache = <&L2>;
0115 clocks = <&clk_controller 2>;
0116 clock-names = "cpu";
0117 cpu-supply = <&cpu_supply2>;
0118 operating-points-v2 = <&cpu_opp_table>;
0119 };
0120
0121 cpu@3 {
0122 compatible = "qcom,krait";
0123 device_type = "cpu";
0124 reg = <3>;
0125 next-level-cache = <&L2>;
0126 clocks = <&clk_controller 3>;
0127 clock-names = "cpu";
0128 cpu-supply = <&cpu_supply3>;
0129 operating-points-v2 = <&cpu_opp_table>;
0130 };
0131 };
0132
0133 cpu_opp_table: opp-table {
0134 compatible = "operating-points-v2";
0135
0136 /*
0137 * Missing opp-shared property means CPUs switch DVFS states
0138 * independently.
0139 */
0140
0141 opp-1000000000 {
0142 opp-hz = /bits/ 64 <1000000000>;
0143 opp-microvolt = <975000 970000 985000>;
0144 opp-microamp = <70000>;
0145 clock-latency-ns = <300000>;
0146 opp-suspend;
0147 };
0148 opp-1100000000 {
0149 opp-hz = /bits/ 64 <1100000000>;
0150 opp-microvolt = <1000000 980000 1010000>;
0151 opp-microamp = <80000>;
0152 clock-latency-ns = <310000>;
0153 };
0154 opp-1200000000 {
0155 opp-hz = /bits/ 64 <1200000000>;
0156 opp-microvolt = <1025000>;
0157 opp-microamp = <90000>;
0158 lock-latency-ns = <290000>;
0159 turbo-mode;
0160 };
0161 };
0162
0163 - |
0164 /*
0165 * Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
0166 * DVFS state together.
0167 */
0168 cpus {
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171
0172 cpu@0 {
0173 compatible = "arm,cortex-a7";
0174 device_type = "cpu";
0175 reg = <0>;
0176 next-level-cache = <&L2>;
0177 clocks = <&clk_controller 0>;
0178 clock-names = "cpu";
0179 cpu-supply = <&cpu_supply0>;
0180 operating-points-v2 = <&cluster0_opp>;
0181 };
0182
0183 cpu@1 {
0184 compatible = "arm,cortex-a7";
0185 device_type = "cpu";
0186 reg = <1>;
0187 next-level-cache = <&L2>;
0188 clocks = <&clk_controller 0>;
0189 clock-names = "cpu";
0190 cpu-supply = <&cpu_supply0>;
0191 operating-points-v2 = <&cluster0_opp>;
0192 };
0193
0194 cpu@100 {
0195 compatible = "arm,cortex-a15";
0196 device_type = "cpu";
0197 reg = <100>;
0198 next-level-cache = <&L2>;
0199 clocks = <&clk_controller 1>;
0200 clock-names = "cpu";
0201 cpu-supply = <&cpu_supply1>;
0202 operating-points-v2 = <&cluster1_opp>;
0203 };
0204
0205 cpu@101 {
0206 compatible = "arm,cortex-a15";
0207 device_type = "cpu";
0208 reg = <101>;
0209 next-level-cache = <&L2>;
0210 clocks = <&clk_controller 1>;
0211 clock-names = "cpu";
0212 cpu-supply = <&cpu_supply1>;
0213 operating-points-v2 = <&cluster1_opp>;
0214 };
0215 };
0216
0217 cluster0_opp: opp-table-0 {
0218 compatible = "operating-points-v2";
0219 opp-shared;
0220
0221 opp-1000000000 {
0222 opp-hz = /bits/ 64 <1000000000>;
0223 opp-microvolt = <975000 970000 985000>;
0224 opp-microamp = <70000>;
0225 clock-latency-ns = <300000>;
0226 opp-suspend;
0227 };
0228 opp-1100000000 {
0229 opp-hz = /bits/ 64 <1100000000>;
0230 opp-microvolt = <1000000 980000 1010000>;
0231 opp-microamp = <80000>;
0232 clock-latency-ns = <310000>;
0233 };
0234 opp-1200000000 {
0235 opp-hz = /bits/ 64 <1200000000>;
0236 opp-microvolt = <1025000>;
0237 opp-microamp = <90000>;
0238 clock-latency-ns = <290000>;
0239 turbo-mode;
0240 };
0241 };
0242
0243 cluster1_opp: opp-table-1 {
0244 compatible = "operating-points-v2";
0245 opp-shared;
0246
0247 opp-1300000000 {
0248 opp-hz = /bits/ 64 <1300000000>;
0249 opp-microvolt = <1050000 1045000 1055000>;
0250 opp-microamp = <95000>;
0251 clock-latency-ns = <400000>;
0252 opp-suspend;
0253 };
0254 opp-1400000000 {
0255 opp-hz = /bits/ 64 <1400000000>;
0256 opp-microvolt = <1075000>;
0257 opp-microamp = <100000>;
0258 clock-latency-ns = <400000>;
0259 };
0260 opp-1500000000 {
0261 opp-hz = /bits/ 64 <1500000000>;
0262 opp-microvolt = <1100000 1010000 1110000>;
0263 opp-microamp = <95000>;
0264 clock-latency-ns = <400000>;
0265 turbo-mode;
0266 };
0267 };
0268
0269 - |
0270 /* Example 4: Handling multiple regulators */
0271 cpus {
0272 #address-cells = <1>;
0273 #size-cells = <0>;
0274
0275 cpu@0 {
0276 compatible = "foo,cpu-type";
0277 device_type = "cpu";
0278 reg = <0>;
0279
0280 vcc0-supply = <&cpu_supply0>;
0281 vcc1-supply = <&cpu_supply1>;
0282 vcc2-supply = <&cpu_supply2>;
0283 operating-points-v2 = <&cpu0_opp_table4>;
0284 };
0285 };
0286
0287 cpu0_opp_table4: opp-table-0 {
0288 compatible = "operating-points-v2";
0289 opp-shared;
0290
0291 opp-1000000000 {
0292 opp-hz = /bits/ 64 <1000000000>;
0293 opp-microvolt = <970000>, /* Supply 0 */
0294 <960000>, /* Supply 1 */
0295 <960000>; /* Supply 2 */
0296 opp-microamp = <70000>, /* Supply 0 */
0297 <70000>, /* Supply 1 */
0298 <70000>; /* Supply 2 */
0299 clock-latency-ns = <300000>;
0300 };
0301
0302 /* OR */
0303
0304 opp-1000000001 {
0305 opp-hz = /bits/ 64 <1000000001>;
0306 opp-microvolt = <975000 970000 985000>, /* Supply 0 */
0307 <965000 960000 975000>, /* Supply 1 */
0308 <965000 960000 975000>; /* Supply 2 */
0309 opp-microamp = <70000>, /* Supply 0 */
0310 <70000>, /* Supply 1 */
0311 <70000>; /* Supply 2 */
0312 clock-latency-ns = <300000>;
0313 };
0314
0315 /* OR */
0316
0317 opp-1000000002 {
0318 opp-hz = /bits/ 64 <1000000002>;
0319 opp-microvolt = <975000 970000 985000>, /* Supply 0 */
0320 <965000 960000 975000>, /* Supply 1 */
0321 <965000 960000 975000>; /* Supply 2 */
0322 opp-microamp = <70000>, /* Supply 0 */
0323 <0>, /* Supply 1 doesn't need this */
0324 <70000>; /* Supply 2 */
0325 clock-latency-ns = <300000>;
0326 };
0327 };
0328
0329 - |
0330 /*
0331 * Example 5: opp-supported-hw
0332 * (example: three level hierarchy of versions: cuts, substrate and process)
0333 */
0334 cpus {
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337
0338 cpu@0 {
0339 compatible = "arm,cortex-a7";
0340 device_type = "cpu";
0341 reg = <0>;
0342 cpu-supply = <&cpu_supply>;
0343 operating-points-v2 = <&cpu0_opp_table_slow>;
0344 };
0345 };
0346
0347 cpu0_opp_table_slow: opp-table {
0348 compatible = "operating-points-v2";
0349 opp-shared;
0350
0351 opp-600000000 {
0352 /*
0353 * Supports all substrate and process versions for 0xF
0354 * cuts, i.e. only first four cuts.
0355 */
0356 opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>;
0357 opp-hz = /bits/ 64 <600000000>;
0358 };
0359
0360 opp-800000000 {
0361 /*
0362 * Supports:
0363 * - cuts: only one, 6th cut (represented by 6th bit).
0364 * - substrate: supports 16 different substrate versions
0365 * - process: supports 9 different process versions
0366 */
0367 opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>;
0368 opp-hz = /bits/ 64 <800000000>;
0369 };
0370
0371 opp-900000000 {
0372 /*
0373 * Supports:
0374 * - All cuts and substrate where process version is 0x2.
0375 * - All cuts and process where substrate version is 0x2.
0376 */
0377 opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>,
0378 <0xFFFFFFFF 0x01 0xFFFFFFFF>;
0379 opp-hz = /bits/ 64 <900000000>;
0380 };
0381 };
0382
0383 - |
0384 /*
0385 * Example 6: opp-microvolt-<name>, opp-microamp-<name>:
0386 * (example: device with two possible microvolt ranges: slow and fast)
0387 */
0388 cpus {
0389 #address-cells = <1>;
0390 #size-cells = <0>;
0391
0392 cpu@0 {
0393 compatible = "arm,cortex-a7";
0394 device_type = "cpu";
0395 reg = <0>;
0396 operating-points-v2 = <&cpu0_opp_table6>;
0397 };
0398 };
0399
0400 cpu0_opp_table6: opp-table-0 {
0401 compatible = "operating-points-v2";
0402 opp-shared;
0403
0404 opp-1000000000 {
0405 opp-hz = /bits/ 64 <1000000000>;
0406 opp-microvolt-slow = <915000 900000 925000>;
0407 opp-microvolt-fast = <975000 970000 985000>;
0408 opp-microamp-slow = <70000>;
0409 opp-microamp-fast = <71000>;
0410 };
0411
0412 opp-1200000000 {
0413 opp-hz = /bits/ 64 <1200000000>;
0414 opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
0415 <925000 910000 935000>; /* Supply vcc1 */
0416 opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
0417 <965000 960000 975000>; /* Supply vcc1 */
0418 opp-microamp = <70000>; /* Will be used for both slow/fast */
0419 };
0420 };
0421
0422 - |
0423 /*
0424 * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
0425 * distinct clock controls but two sets of clock/voltage/current lines.
0426 */
0427 cpus {
0428 #address-cells = <2>;
0429 #size-cells = <0>;
0430
0431 cpu@0 {
0432 compatible = "arm,cortex-a53";
0433 device_type = "cpu";
0434 reg = <0x0 0x100>;
0435 next-level-cache = <&A53_L2>;
0436 clocks = <&dvfs_controller 0>;
0437 operating-points-v2 = <&cpu_opp0_table>;
0438 };
0439 cpu@1 {
0440 compatible = "arm,cortex-a53";
0441 device_type = "cpu";
0442 reg = <0x0 0x101>;
0443 next-level-cache = <&A53_L2>;
0444 clocks = <&dvfs_controller 1>;
0445 operating-points-v2 = <&cpu_opp0_table>;
0446 };
0447 cpu@2 {
0448 compatible = "arm,cortex-a53";
0449 device_type = "cpu";
0450 reg = <0x0 0x102>;
0451 next-level-cache = <&A53_L2>;
0452 clocks = <&dvfs_controller 2>;
0453 operating-points-v2 = <&cpu_opp1_table>;
0454 };
0455 cpu@3 {
0456 compatible = "arm,cortex-a53";
0457 device_type = "cpu";
0458 reg = <0x0 0x103>;
0459 next-level-cache = <&A53_L2>;
0460 clocks = <&dvfs_controller 3>;
0461 operating-points-v2 = <&cpu_opp1_table>;
0462 };
0463
0464 };
0465
0466 cpu_opp0_table: opp-table-0 {
0467 compatible = "operating-points-v2";
0468 opp-shared;
0469 };
0470
0471 cpu_opp1_table: opp-table-1 {
0472 compatible = "operating-points-v2";
0473 opp-shared;
0474 };
0475 ...
