0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Technologies, Inc. NVMEM OPP bindings
0008
0009 maintainers:
0010 - Ilia Lin <ilia.lin@kernel.org>
0011
0012 allOf:
0013 - $ref: opp-v2-base.yaml#
0014
0015 description: |
0016 In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
0017 the CPU frequencies subset and voltage value of each OPP varies based on
0018 the silicon variant in use.
0019 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
0020 defines the voltage and frequency value based on the speedbin blown in
0021 the efuse combination.
0022 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
0023 the OPP framework with required information (existing HW bitmap).
0024 This is used to determine the voltage and frequency value for each OPP of
0025 operating-points-v2 table when it is parsed by the OPP framework.
0026
0027 properties:
0028 compatible:
0029 const: operating-points-v2-kryo-cpu
0030
0031 nvmem-cells:
0032 description: |
0033 A phandle pointing to a nvmem-cells node representing the
0034 efuse registers that has information about the
0035 speedbin that is used to select the right frequency/voltage
0036 value pair.
0037
0038 opp-shared: true
0039
0040 patternProperties:
0041 '^opp-?[0-9]+$':
0042 type: object
0043 additionalProperties: false
0044
0045 properties:
0046 opp-hz: true
0047
0048 opp-microvolt: true
0049
0050 opp-supported-hw:
0051 description: |
0052 A single 32 bit bitmap value, representing compatible HW.
0053 Bitmap:
0054 0: MSM8996, speedbin 0
0055 1: MSM8996, speedbin 1
0056 2: MSM8996, speedbin 2
0057 3-31: unused
0058 maximum: 0x7
0059
0060 clock-latency-ns: true
0061
0062 required-opps: true
0063
0064 required:
0065 - opp-hz
0066
0067 required:
0068 - compatible
0069
0070 if:
0071 required:
0072 - nvmem-cells
0073 then:
0074 patternProperties:
0075 '^opp-?[0-9]+$':
0076 required:
0077 - opp-supported-hw
0078
0079 additionalProperties: false
0080
0081 examples:
0082 - |
0083 / {
0084 model = "Qualcomm Technologies, Inc. DB820c";
0085 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
0086 #address-cells = <2>;
0087 #size-cells = <2>;
0088
0089 cpus {
0090 #address-cells = <2>;
0091 #size-cells = <0>;
0092
0093 CPU0: cpu@0 {
0094 device_type = "cpu";
0095 compatible = "qcom,kryo";
0096 reg = <0x0 0x0>;
0097 enable-method = "psci";
0098 cpu-idle-states = <&CPU_SLEEP_0>;
0099 capacity-dmips-mhz = <1024>;
0100 clocks = <&kryocc 0>;
0101 operating-points-v2 = <&cluster0_opp>;
0102 power-domains = <&cpr>;
0103 power-domain-names = "cpr";
0104 #cooling-cells = <2>;
0105 next-level-cache = <&L2_0>;
0106 L2_0: l2-cache {
0107 compatible = "cache";
0108 cache-level = <2>;
0109 };
0110 };
0111
0112 CPU1: cpu@1 {
0113 device_type = "cpu";
0114 compatible = "qcom,kryo";
0115 reg = <0x0 0x1>;
0116 enable-method = "psci";
0117 cpu-idle-states = <&CPU_SLEEP_0>;
0118 capacity-dmips-mhz = <1024>;
0119 clocks = <&kryocc 0>;
0120 operating-points-v2 = <&cluster0_opp>;
0121 power-domains = <&cpr>;
0122 power-domain-names = "cpr";
0123 #cooling-cells = <2>;
0124 next-level-cache = <&L2_0>;
0125 };
0126
0127 CPU2: cpu@100 {
0128 device_type = "cpu";
0129 compatible = "qcom,kryo";
0130 reg = <0x0 0x100>;
0131 enable-method = "psci";
0132 cpu-idle-states = <&CPU_SLEEP_0>;
0133 capacity-dmips-mhz = <1024>;
0134 clocks = <&kryocc 1>;
0135 operating-points-v2 = <&cluster1_opp>;
0136 power-domains = <&cpr>;
0137 power-domain-names = "cpr";
0138 #cooling-cells = <2>;
0139 next-level-cache = <&L2_1>;
0140 L2_1: l2-cache {
0141 compatible = "cache";
0142 cache-level = <2>;
0143 };
0144 };
0145
0146 CPU3: cpu@101 {
0147 device_type = "cpu";
0148 compatible = "qcom,kryo";
0149 reg = <0x0 0x101>;
0150 enable-method = "psci";
0151 cpu-idle-states = <&CPU_SLEEP_0>;
0152 capacity-dmips-mhz = <1024>;
0153 clocks = <&kryocc 1>;
0154 operating-points-v2 = <&cluster1_opp>;
0155 power-domains = <&cpr>;
0156 power-domain-names = "cpr";
0157 #cooling-cells = <2>;
0158 next-level-cache = <&L2_1>;
0159 };
0160
0161 cpu-map {
0162 cluster0 {
0163 core0 {
0164 cpu = <&CPU0>;
0165 };
0166
0167 core1 {
0168 cpu = <&CPU1>;
0169 };
0170 };
0171
0172 cluster1 {
0173 core0 {
0174 cpu = <&CPU2>;
0175 };
0176
0177 core1 {
0178 cpu = <&CPU3>;
0179 };
0180 };
0181 };
0182 };
0183
0184 cluster0_opp: opp-table-0 {
0185 compatible = "operating-points-v2-kryo-cpu";
0186 nvmem-cells = <&speedbin_efuse>;
0187 opp-shared;
0188
0189 opp-307200000 {
0190 opp-hz = /bits/ 64 <307200000>;
0191 opp-microvolt = <905000 905000 1140000>;
0192 opp-supported-hw = <0x7>;
0193 clock-latency-ns = <200000>;
0194 required-opps = <&cpr_opp1>;
0195 };
0196 opp-1401600000 {
0197 opp-hz = /bits/ 64 <1401600000>;
0198 opp-microvolt = <1140000 905000 1140000>;
0199 opp-supported-hw = <0x5>;
0200 clock-latency-ns = <200000>;
0201 required-opps = <&cpr_opp2>;
0202 };
0203 opp-1593600000 {
0204 opp-hz = /bits/ 64 <1593600000>;
0205 opp-microvolt = <1140000 905000 1140000>;
0206 opp-supported-hw = <0x1>;
0207 clock-latency-ns = <200000>;
0208 required-opps = <&cpr_opp3>;
0209 };
0210 };
0211
0212 cluster1_opp: opp-table-1 {
0213 compatible = "operating-points-v2-kryo-cpu";
0214 nvmem-cells = <&speedbin_efuse>;
0215 opp-shared;
0216
0217 opp-307200000 {
0218 opp-hz = /bits/ 64 <307200000>;
0219 opp-microvolt = <905000 905000 1140000>;
0220 opp-supported-hw = <0x7>;
0221 clock-latency-ns = <200000>;
0222 required-opps = <&cpr_opp1>;
0223 };
0224 opp-1804800000 {
0225 opp-hz = /bits/ 64 <1804800000>;
0226 opp-microvolt = <1140000 905000 1140000>;
0227 opp-supported-hw = <0x6>;
0228 clock-latency-ns = <200000>;
0229 required-opps = <&cpr_opp4>;
0230 };
0231 opp-1900800000 {
0232 opp-hz = /bits/ 64 <1900800000>;
0233 opp-microvolt = <1140000 905000 1140000>;
0234 opp-supported-hw = <0x4>;
0235 clock-latency-ns = <200000>;
0236 required-opps = <&cpr_opp5>;
0237 };
0238 opp-2150400000 {
0239 opp-hz = /bits/ 64 <2150400000>;
0240 opp-microvolt = <1140000 905000 1140000>;
0241 opp-supported-hw = <0x1>;
0242 clock-latency-ns = <200000>;
0243 required-opps = <&cpr_opp6>;
0244 };
0245 };
0246
0247 smem {
0248 compatible = "qcom,smem";
0249 memory-region = <&smem_mem>;
0250 hwlocks = <&tcsr_mutex 3>;
0251 };
0252
0253 soc {
0254 #address-cells = <1>;
0255 #size-cells = <1>;
0256
0257 qfprom: qfprom@74000 {
0258 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
0259 reg = <0x00074000 0x8ff>;
0260 #address-cells = <1>;
0261 #size-cells = <1>;
0262
0263 speedbin_efuse: speedbin@133 {
0264 reg = <0x133 0x1>;
0265 bits = <5 3>;
0266 };
0267 };
0268 };
0269 };
