0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner H6 CPU OPP Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 description: |
0014 For some SoCs, the CPU frequency subset and voltage value of each
0015 OPP varies based on the silicon variant in use. Allwinner Process
0016 Voltage Scaling Tables defines the voltage and frequency value based
0017 on the speedbin blown in the efuse combination. The
0018 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
0019 provide the OPP framework with required information.
0020
0021 allOf:
0022 - $ref: opp-v2-base.yaml#
0023
0024 properties:
0025 compatible:
0026 const: allwinner,sun50i-h6-operating-points
0027
0028 nvmem-cells:
0029 description: |
0030 A phandle pointing to a nvmem-cells node representing the efuse
0031 registers that has information about the speedbin that is used
0032 to select the right frequency/voltage value pair. Please refer
0033 the for nvmem-cells bindings
0034 Documentation/devicetree/bindings/nvmem/nvmem.txt and also
0035 examples below.
0036
0037 opp-shared: true
0038
0039 required:
0040 - compatible
0041 - nvmem-cells
0042
0043 patternProperties:
0044 "opp-[0-9]+":
0045 type: object
0046
0047 properties:
0048 opp-hz: true
0049 clock-latency-ns: true
0050
0051 patternProperties:
0052 "opp-microvolt-.*": true
0053
0054 required:
0055 - opp-hz
0056 - opp-microvolt-speed0
0057 - opp-microvolt-speed1
0058 - opp-microvolt-speed2
0059
0060 unevaluatedProperties: false
0061
0062 additionalProperties: false
0063
0064 examples:
0065 - |
0066 cpu_opp_table: opp-table {
0067 compatible = "allwinner,sun50i-h6-operating-points";
0068 nvmem-cells = <&speedbin_efuse>;
0069 opp-shared;
0070
0071 opp-480000000 {
0072 clock-latency-ns = <244144>; /* 8 32k periods */
0073 opp-hz = /bits/ 64 <480000000>;
0074
0075 opp-microvolt-speed0 = <880000>;
0076 opp-microvolt-speed1 = <820000>;
0077 opp-microvolt-speed2 = <800000>;
0078 };
0079
0080 opp-720000000 {
0081 clock-latency-ns = <244144>; /* 8 32k periods */
0082 opp-hz = /bits/ 64 <720000000>;
0083
0084 opp-microvolt-speed0 = <880000>;
0085 opp-microvolt-speed1 = <820000>;
0086 opp-microvolt-speed2 = <800000>;
0087 };
0088
0089 opp-816000000 {
0090 clock-latency-ns = <244144>; /* 8 32k periods */
0091 opp-hz = /bits/ 64 <816000000>;
0092
0093 opp-microvolt-speed0 = <880000>;
0094 opp-microvolt-speed1 = <820000>;
0095 opp-microvolt-speed2 = <800000>;
0096 };
0097
0098 opp-888000000 {
0099 clock-latency-ns = <244144>; /* 8 32k periods */
0100 opp-hz = /bits/ 64 <888000000>;
0101
0102 opp-microvolt-speed0 = <940000>;
0103 opp-microvolt-speed1 = <820000>;
0104 opp-microvolt-speed2 = <800000>;
0105 };
0106
0107 opp-1080000000 {
0108 clock-latency-ns = <244144>; /* 8 32k periods */
0109 opp-hz = /bits/ 64 <1080000000>;
0110
0111 opp-microvolt-speed0 = <1060000>;
0112 opp-microvolt-speed1 = <880000>;
0113 opp-microvolt-speed2 = <840000>;
0114 };
0115
0116 opp-1320000000 {
0117 clock-latency-ns = <244144>; /* 8 32k periods */
0118 opp-hz = /bits/ 64 <1320000000>;
0119
0120 opp-microvolt-speed0 = <1160000>;
0121 opp-microvolt-speed1 = <940000>;
0122 opp-microvolt-speed2 = <900000>;
0123 };
0124
0125 opp-1488000000 {
0126 clock-latency-ns = <244144>; /* 8 32k periods */
0127 opp-hz = /bits/ 64 <1488000000>;
0128
0129 opp-microvolt-speed0 = <1160000>;
0130 opp-microvolt-speed1 = <1000000>;
0131 opp-microvolt-speed2 = <960000>;
0132 };
0133 };
0134
0135 ...
