0001 STMicroelectronics SoC DWMAC glue layer controller
0002
0003 This file documents differences between the core properties in
0004 Documentation/devicetree/bindings/net/stmmac.txt
0005 and what is needed on STi platforms to program the stmmac glue logic.
0006
0007 The device node has following properties.
0008
0009 Required properties:
0010 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
0011 "st,stih407-dwmac", "st,stid127-dwmac".
0012 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
0013 encompases the glue register, and the offset of the control register.
0014 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
0015 register available on STiH407 SoC.
0016 - pinctrl-0: pin-control for all the MII mode supported.
0017
0018 Optional properties:
0019 - resets : phandle pointing to the system reset controller with correct
0020 reset line index for ethernet reset.
0021 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
0022 MAC can generate it.
0023 - st,tx-retime-src: This specifies which clk is wired up to the mac for
0024 retimeing tx lines. This is totally board dependent and can take one of the
0025 posssible values from "txclk", "clk_125" or "clkgen".
0026 If not passed, the internal clock will be used by default.
0027 - sti-ethclk: this is the phy clock.
0028 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
0029 to program the clk retiming.
0030 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
0031 STiH407.
0032
0033 Example:
0034
0035 ethernet0: dwmac@9630000 {
0036 device_type = "network";
0037 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
0038 reg = <0x9630000 0x8000>;
0039 reg-names = "stmmaceth";
0040
0041 st,syscon = <&syscfg_sbc_reg 0x80>;
0042 st,gmac_en;
0043 resets = <&softreset STIH407_ETH1_SOFTRESET>;
0044 reset-names = "stmmaceth";
0045
0046 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
0047 <GIC_SPI 99 IRQ_TYPE_NONE>,
0048 <GIC_SPI 100 IRQ_TYPE_NONE>;
0049 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
0050
0051 snps,pbl = <32>;
0052 snps,mixed-burst;
0053
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&pinctrl_rgmii1>;
0056
0057 clock-names = "stmmaceth", "sti-ethclk";
0058 clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
0059 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
0060 };
