0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Generic register bitfield-based multiplexer controller bindings
0008
0009 maintainers:
0010 - Peter Rosin <peda@axentia.se>
0011
0012 description: |+
0013 Define register bitfields to be used to control multiplexers. The parent
0014 device tree node must be a device node to provide register r/w access.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - reg-mux # parent device of mux controller is not syscon device
0020 - mmio-mux # parent device of mux controller is syscon device
0021
0022 reg: true
0023
0024 '#mux-control-cells':
0025 const: 1
0026
0027 mux-reg-masks:
0028 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0029 items:
0030 items:
0031 - description: register offset
0032 - description: pre-shifted bitfield mask
0033 description: Each entry pair describes a single mux control.
0034
0035 idle-states: true
0036
0037 required:
0038 - compatible
0039 - mux-reg-masks
0040 - '#mux-control-cells'
0041
0042 additionalProperties: false
0043
0044 examples:
0045 - |
0046 /* The parent device of mux controller is not a syscon device. */
0047
0048 #include <dt-bindings/mux/mux.h>
0049
0050 mux-controller {
0051 compatible = "reg-mux";
0052 #mux-control-cells = <1>;
0053 mux-reg-masks =
0054 <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
0055 <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
0056 };
0057
0058 mdio-mux-1 {
0059 compatible = "mdio-mux-multiplexer";
0060 mux-controls = <&mux1 0>;
0061 mdio-parent-bus = <&emdio1>;
0062 #address-cells = <1>;
0063 #size-cells = <0>;
0064
0065 mdio@0 {
0066 reg = <0x0>;
0067 #address-cells = <1>;
0068 #size-cells = <0>;
0069 };
0070
0071 mdio@8 {
0072 reg = <0x8>;
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075 };
0076 };
0077
0078 mdio-mux-2 {
0079 compatible = "mdio-mux-multiplexer";
0080 mux-controls = <&mux1 1>;
0081 mdio-parent-bus = <&emdio2>;
0082 #address-cells = <1>;
0083 #size-cells = <0>;
0084
0085 mdio@0 {
0086 reg = <0x0>;
0087 #address-cells = <1>;
0088 #size-cells = <0>;
0089 };
0090
0091 mdio@1 {
0092 reg = <0x1>;
0093 #address-cells = <1>;
0094 #size-cells = <0>;
0095 };
0096 };
0097
0098 - |
0099 /* The parent device of mux controller is syscon device. */
0100
0101 #include <dt-bindings/mux/mux.h>
0102 syscon@1000 {
0103 reg = <0x1000 0x100>;
0104
0105 mux2: mux-controller {
0106 compatible = "mmio-mux";
0107 #mux-control-cells = <1>;
0108
0109 mux-reg-masks =
0110 <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
0111 <0x3 0x40>; /* 1: reg 0x3, bit 6 */
0112 idle-states = <MUX_IDLE_AS_IS>, <0>;
0113 };
0114 };
0115
0116 video-mux {
0117 compatible = "video-mux";
0118 mux-controls = <&mux2 0>;
0119 #address-cells = <1>;
0120 #size-cells = <0>;
0121
0122 ports {
0123 #address-cells = <1>;
0124 #size-cells = <0>;
0125
0126 /* inputs 0..3 */
0127 port@0 {
0128 reg = <0>;
0129 };
0130 port@1 {
0131 reg = <1>;
0132 };
0133 port@2 {
0134 reg = <2>;
0135 };
0136 port@3 {
0137 reg = <3>;
0138 };
0139
0140 /* output */
0141 port@4 {
0142 reg = <4>;
0143 };
0144 };
0145 };
0146 ...
