0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments GPMC NAND Flash controller.
0008
0009 maintainers:
0010 - Tony Lindgren <tony@atomide.com>
0011 - Roger Quadros <rogerq@kernel.org>
0012
0013 description:
0014 GPMC NAND controller/Flash is represented as a child of the
0015 GPMC controller node.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - enum:
0021 - ti,am64-nand
0022 - ti,omap2-nand
0023
0024 reg:
0025 maxItems: 1
0026
0027 interrupts:
0028 items:
0029 - description: Interrupt for fifoevent
0030 - description: Interrupt for termcount
0031
0032 "#address-cells": true
0033
0034 "#size-cells": true
0035
0036 ti,nand-ecc-opt:
0037 description: Desired ECC algorithm
0038 $ref: /schemas/types.yaml#/definitions/string
0039 enum: [sw, ham1, bch4, bch8, bch16]
0040
0041 ti,nand-xfer-type:
0042 description: Data transfer method between controller and chip.
0043 $ref: /schemas/types.yaml#/definitions/string
0044 enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
0045 default: prefetch-polled
0046
0047 ti,elm-id:
0048 description:
0049 phandle to the ELM (Error Location Module).
0050 $ref: /schemas/types.yaml#/definitions/phandle
0051
0052 nand-bus-width:
0053 description:
0054 Bus width to the NAND chip
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 enum: [8, 16]
0057 default: 8
0058
0059 rb-gpios:
0060 description:
0061 GPIO connection to R/B signal from NAND chip
0062 maxItems: 1
0063
0064 patternProperties:
0065 "@[0-9a-f]+$":
0066 $ref: "/schemas/mtd/partitions/partition.yaml"
0067
0068 allOf:
0069 - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
0070
0071 required:
0072 - compatible
0073 - reg
0074 - ti,nand-ecc-opt
0075
0076 unevaluatedProperties: false
0077
0078 examples:
0079 - |
0080 #include <dt-bindings/interrupt-controller/arm-gic.h>
0081 #include <dt-bindings/gpio/gpio.h>
0082
0083 gpmc: memory-controller@50000000 {
0084 compatible = "ti,am3352-gpmc";
0085 dmas = <&edma 52 0>;
0086 dma-names = "rxtx";
0087 clocks = <&l3s_gclk>;
0088 clock-names = "fck";
0089 reg = <0x50000000 0x2000>;
0090 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0091 gpmc,num-cs = <7>;
0092 gpmc,num-waitpins = <2>;
0093 #address-cells = <2>;
0094 #size-cells = <1>;
0095 interrupt-controller;
0096 #interrupt-cells = <2>;
0097 gpio-controller;
0098 #gpio-cells = <2>;
0099
0100 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
0101 nand@0,0 {
0102 compatible = "ti,omap2-nand";
0103 reg = <0 0 4>; /* device IO registers */
0104 interrupt-parent = <&gpmc>;
0105 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0106 <1 IRQ_TYPE_NONE>; /* termcount */
0107 ti,nand-xfer-type = "prefetch-dma";
0108 ti,nand-ecc-opt = "bch16";
0109 ti,elm-id = <&elm>;
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112
0113 /* NAND generic properties */
0114 nand-bus-width = <8>;
0115 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
0116
0117 /* GPMC properties*/
0118 gpmc,device-width = <1>;
0119
0120 partition@0 {
0121 label = "NAND.SPL";
0122 reg = <0x00000000 0x00040000>;
0123 };
0124 partition@1 {
0125 label = "NAND.SPL.backup1";
0126 reg = <0x00040000 0x00040000>;
0127 };
0128 };
0129 };
