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OSCL-LXR

 
 

    


0001 * Oxford Semiconductor OXNAS NAND Controller
0002 
0003 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
0004 
0005 Required properties:
0006  - compatible: "oxsemi,ox820-nand"
0007  - reg: Base address and length for NAND mapped memory.
0008 
0009 Optional Properties:
0010  - clocks: phandle to the NAND gate clock if needed.
0011  - resets: phandle to the NAND reset control if needed.
0012 
0013 Example:
0014 
0015 nandc: nand-controller@41000000 {
0016         compatible = "oxsemi,ox820-nand";
0017         reg = <0x41000000 0x100000>;
0018         clocks = <&stdclk CLK_820_NAND>;
0019         resets = <&reset RESET_NAND>;
0020         #address-cells = <1>;
0021         #size-cells = <0>;
0022 
0023         nand@0 {
0024                 reg = <0>;
0025                 #address-cells = <1>;
0026                 #size-cells = <1>;
0027                 nand-ecc-mode = "soft";
0028                 nand-ecc-algo = "hamming";
0029 
0030                 partition@0 {
0031                         label = "boot";
0032                         reg = <0x00000000 0x00e00000>;
0033                         read-only;
0034                 };
0035 
0036                 partition@e00000 {
0037                         label = "ubi";
0038                         reg = <0x00e00000 0x07200000>;
0039                 };
0040         };
0041 };