0001 * NXP SPI Flash Interface (SPIFI)
0002
0003 NXP SPIFI is a specialized SPI interface for serial Flash devices.
0004 It supports one Flash device with 1-, 2- and 4-bits width in SPI
0005 mode 0 or 3. The controller operates in either command or memory
0006 mode. In memory mode the Flash is accessible from the CPU as
0007 normal memory.
0008
0009 Required properties:
0010 - compatible : Should be "nxp,lpc1773-spifi"
0011 - reg : the first contains the register location and length,
0012 the second contains the memory mapping address and length
0013 - reg-names: Should contain the reg names "spifi" and "flash"
0014 - interrupts : Should contain the interrupt for the device
0015 - clocks : The clocks needed by the SPIFI controller
0016 - clock-names : Should contain the clock names "spifi" and "reg"
0017
0018 Optional properties:
0019 - resets : phandle + reset specifier
0020
0021 The SPI Flash must be a child of the SPIFI node and must have a
0022 compatible property as specified in bindings/mtd/jedec,spi-nor.txt
0023
0024 Optionally it can also contain the following properties.
0025 - spi-cpol : Controller only supports mode 0 and 3 so either
0026 both spi-cpol and spi-cpha should be present or
0027 none of them
0028 - spi-cpha : See above
0029 - spi-rx-bus-width : Used to select how many pins that are used
0030 for input on the controller
0031
0032 See bindings/spi/spi-bus.txt for more information.
0033
0034 Example:
0035 spifi: spifi@40003000 {
0036 compatible = "nxp,lpc1773-spifi";
0037 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
0038 reg-names = "spifi", "flash";
0039 interrupts = <30>;
0040 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
0041 clock-names = "spifi", "reg";
0042 resets = <&rgu 53>;
0043
0044 flash@0 {
0045 compatible = "jedec,spi-nor";
0046 spi-cpol;
0047 spi-cpha;
0048 spi-rx-bus-width = <4>;
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051
0052 partition@0 {
0053 label = "data";
0054 reg = <0 0x200000>;
0055 };
0056 };
0057 };
0058
