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0001 NVIDIA Tegra NAND Flash controller
0002 
0003 Required properties:
0004 - compatible: Must be one of:
0005   - "nvidia,tegra20-nand"
0006 - reg: MMIO address range
0007 - interrupts: interrupt output of the NFC controller
0008 - clocks: Must contain an entry for each entry in clock-names.
0009   See ../clocks/clock-bindings.txt for details.
0010 - clock-names: Must include the following entries:
0011   - nand
0012 - resets: Must contain an entry for each entry in reset-names.
0013   See ../reset/reset.txt for details.
0014 - reset-names: Must include the following entries:
0015   - nand
0016 
0017 Optional children nodes:
0018 Individual NAND chips are children of the NAND controller node. Currently
0019 only one NAND chip supported.
0020 
0021 Required children node properties:
0022 - reg: An integer ranging from 1 to 6 representing the CS line to use.
0023 
0024 Optional children node properties:
0025 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
0026                  "hw" is supported.
0027 - nand-ecc-algo: string, algorithm of NAND ECC.
0028                  Supported values with "hw" ECC mode are: "rs", "bch".
0029 - nand-bus-width : See nand-controller.yaml
0030 - nand-on-flash-bbt: See nand-controller.yaml
0031 - nand-ecc-strength: integer representing the number of bits to correct
0032                      per ECC step (always 512). Supported strength using HW ECC
0033                      modes are:
0034                      - RS: 4, 6, 8
0035                      - BCH: 4, 8, 14, 16
0036 - nand-ecc-maximize: See nand-controller.yaml
0037 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
0038                        are chosen.
0039 - wp-gpios: GPIO specifier for the write protect pin.
0040 
0041 Optional child node of NAND chip nodes:
0042 Partitions: see partition.txt
0043 
0044   Example:
0045         nand-controller@70008000 {
0046                 compatible = "nvidia,tegra20-nand";
0047                 reg = <0x70008000 0x100>;
0048                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0049                 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
0050                 clock-names = "nand";
0051                 resets = <&tegra_car 13>;
0052                 reset-names = "nand";
0053 
0054                 nand@0 {
0055                         reg = <0>;
0056                         #address-cells = <1>;
0057                         #size-cells = <1>;
0058                         nand-bus-width = <8>;
0059                         nand-on-flash-bbt;
0060                         nand-ecc-algo = "bch";
0061                         nand-ecc-strength = <8>;
0062                         wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
0063                 };
0064         };