0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NAND Chip and NAND Controller Generic Binding
0008
0009 maintainers:
0010 - Miquel Raynal <miquel.raynal@bootlin.com>
0011 - Richard Weinberger <richard@nod.at>
0012
0013 description: |
0014 The NAND controller should be represented with its own DT node, and
0015 all NAND chips attached to this controller should be defined as
0016 children nodes of the NAND controller. This representation should be
0017 enforced even for simple controllers supporting only one chip.
0018
0019 The ECC strength and ECC step size properties define the user
0020 desires in terms of correction capability of a controller. Together,
0021 they request the ECC engine to correct {strength} bit errors per
0022 {size} bytes.
0023
0024 The interpretation of these parameters is implementation-defined, so
0025 not all implementations must support all possible
0026 combinations. However, implementations are encouraged to further
0027 specify the value(s) they support.
0028
0029 properties:
0030 $nodename:
0031 pattern: "^nand-controller(@.*)?"
0032
0033 "#address-cells":
0034 const: 1
0035
0036 "#size-cells":
0037 const: 0
0038
0039 ranges: true
0040
0041 cs-gpios:
0042 description:
0043 Array of chip-select available to the controller. The first
0044 entries are a 1:1 mapping of the available chip-select on the
0045 NAND controller (even if they are not used). As many additional
0046 chip-select as needed may follow and should be phandles of GPIO
0047 lines. 'reg' entries of the NAND chip subnodes become indexes of
0048 this array when this property is present.
0049 minItems: 1
0050 maxItems: 8
0051
0052 patternProperties:
0053 "^nand@[a-f0-9]$":
0054 type: object
0055 $ref: "nand-chip.yaml#"
0056
0057 properties:
0058 reg:
0059 description:
0060 Contains the chip-select IDs.
0061
0062 nand-ecc-placement:
0063 description:
0064 Location of the ECC bytes. This location is unknown by default
0065 but can be explicitly set to "oob", if all ECC bytes are
0066 known to be stored in the OOB area, or "interleaved" if ECC
0067 bytes will be interleaved with regular data in the main area.
0068 $ref: /schemas/types.yaml#/definitions/string
0069 enum: [ oob, interleaved ]
0070
0071 nand-bus-width:
0072 description:
0073 Bus width to the NAND chip
0074 $ref: /schemas/types.yaml#/definitions/uint32
0075 enum: [8, 16]
0076 default: 8
0077
0078 nand-on-flash-bbt:
0079 description:
0080 With this property, the OS will search the device for a Bad
0081 Block Table (BBT). If not found, it will create one, reserve
0082 a few blocks at the end of the device to store it and update
0083 it as the device ages. Otherwise, the out-of-band area of a
0084 few pages of all the blocks will be scanned at boot time to
0085 find Bad Block Markers (BBM). These markers will help to
0086 build a volatile BBT in RAM.
0087 $ref: /schemas/types.yaml#/definitions/flag
0088
0089 nand-ecc-maximize:
0090 description:
0091 Whether or not the ECC strength should be maximized. The
0092 maximum ECC strength is both controller and chip
0093 dependent. The ECC engine has to select the ECC config
0094 providing the best strength and taking the OOB area size
0095 constraint into account. This is particularly useful when
0096 only the in-band area is used by the upper layers, and you
0097 want to make your NAND as reliable as possible.
0098 $ref: /schemas/types.yaml#/definitions/flag
0099
0100 nand-is-boot-medium:
0101 description:
0102 Whether or not the NAND chip is a boot medium. Drivers might
0103 use this information to select ECC algorithms supported by
0104 the boot ROM or similar restrictions.
0105 $ref: /schemas/types.yaml#/definitions/flag
0106
0107 nand-rb:
0108 description:
0109 Contains the native Ready/Busy IDs.
0110 $ref: /schemas/types.yaml#/definitions/uint32-array
0111
0112 rb-gpios:
0113 description:
0114 Contains one or more GPIO descriptor (the numper of descriptor
0115 depends on the number of R/B pins exposed by the flash) for the
0116 Ready/Busy pins. Active state refers to the NAND ready state and
0117 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
0118
0119 wp-gpios:
0120 description:
0121 Contains one GPIO descriptor for the Write Protect pin.
0122 Active state refers to the NAND Write Protect state and should be
0123 set to GPIOD_ACTIVE_LOW unless the signal is inverted.
0124 maxItems: 1
0125
0126 required:
0127 - reg
0128
0129 required:
0130 - "#address-cells"
0131 - "#size-cells"
0132
0133 additionalProperties: true
0134
0135 examples:
0136 - |
0137 nand-controller {
0138 #address-cells = <1>;
0139 #size-cells = <0>;
0140 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
0141
0142 /* controller specific properties */
0143
0144 nand@0 {
0145 reg = <0>; /* Native CS */
0146 /* NAND chip specific properties */
0147 };
0148
0149 nand@1 {
0150 reg = <1>; /* GPIO CS */
0151 };
0152 };
