0001 MTK SoCs NAND FLASH controller (NFC) DT binding
0002
0003 This file documents the device tree bindings for MTK SoCs NAND controllers.
0004 The functional split of the controller requires two drivers to operate:
0005 the nand controller interface driver and the ECC engine driver.
0006
0007 The hardware description for both devices must be captured as device
0008 tree nodes.
0009
0010 1) NFC NAND Controller Interface (NFI):
0011 =======================================
0012
0013 The first part of NFC is NAND Controller Interface (NFI) HW.
0014 Required NFI properties:
0015 - compatible: Should be one of
0016 "mediatek,mt2701-nfc",
0017 "mediatek,mt2712-nfc",
0018 "mediatek,mt7622-nfc".
0019 - reg: Base physical address and size of NFI.
0020 - interrupts: Interrupts of NFI.
0021 - clocks: NFI required clocks.
0022 - clock-names: NFI clocks internal name.
0023 - ecc-engine: Required ECC Engine node.
0024 - #address-cells: NAND chip index, should be 1.
0025 - #size-cells: Should be 0.
0026
0027 Example:
0028
0029 nandc: nfi@1100d000 {
0030 compatible = "mediatek,mt2701-nfc";
0031 reg = <0 0x1100d000 0 0x1000>;
0032 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
0033 clocks = <&pericfg CLK_PERI_NFI>,
0034 <&pericfg CLK_PERI_NFI_PAD>;
0035 clock-names = "nfi_clk", "pad_clk";
0036 ecc-engine = <&bch>;
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039 };
0040
0041 Platform related properties, should be set in {platform_name}.dts:
0042 - children nodes: NAND chips.
0043
0044 Children nodes properties:
0045 - reg: Chip Select Signal, default 0.
0046 Set as reg = <0>, <1> when need 2 CS.
0047 Optional:
0048 - nand-on-flash-bbt: Store BBT on NAND Flash.
0049 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
0050 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
0051 valid values:
0052 512 and 1024 on mt2701 and mt2712.
0053 512 only on mt7622.
0054 1024 is recommended for large page NANDs.
0055 - nand-ecc-strength: Number of bits to correct per ECC step.
0056 The valid values that each controller supports:
0057 mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
0058 32, 36, 40, 44, 48, 52, 56, 60.
0059 mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
0060 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
0061 mt7622: 4, 6, 8, 10, 12, 14, 16.
0062 The strength should be calculated as follows:
0063 E = (S - F) * 8 / B
0064 S = O / (P / Q)
0065 E : nand-ecc-strength.
0066 S : spare size per sector.
0067 F : FDM size, should be in the range [1,8].
0068 It is used to store free oob data.
0069 O : oob size.
0070 P : page size.
0071 Q : nand-ecc-step-size.
0072 B : number of parity bits needed to correct
0073 1 bitflip.
0074 According to MTK NAND controller design,
0075 this number depends on max ecc step size
0076 that MTK NAND controller supports.
0077 If max ecc step size supported is 1024,
0078 then it should be always 14. And if max
0079 ecc step size is 512, then it should be
0080 always 13.
0081 If the result does not match any one of the listed
0082 choices above, please select the smaller valid value from
0083 the list.
0084 (otherwise the driver will do the adjustment at runtime)
0085 - pinctrl-names: Default NAND pin GPIO setting name.
0086 - pinctrl-0: GPIO setting node.
0087
0088 Example:
0089 &pio {
0090 nand_pins_default: nanddefault {
0091 pins_dat {
0092 pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
0093 <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
0094 <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
0095 <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
0096 <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
0097 <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
0098 <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
0099 <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
0100 <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
0101 input-enable;
0102 drive-strength = <MTK_DRIVE_8mA>;
0103 bias-pull-up;
0104 };
0105
0106 pins_we {
0107 pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
0108 drive-strength = <MTK_DRIVE_8mA>;
0109 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
0110 };
0111
0112 pins_ale {
0113 pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
0114 drive-strength = <MTK_DRIVE_8mA>;
0115 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0116 };
0117 };
0118 };
0119
0120 &nandc {
0121 status = "okay";
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&nand_pins_default>;
0124 nand@0 {
0125 reg = <0>;
0126 nand-on-flash-bbt;
0127 nand-ecc-mode = "hw";
0128 nand-ecc-strength = <24>;
0129 nand-ecc-step-size = <1024>;
0130 };
0131 };
0132
0133 NAND chip optional subnodes:
0134 - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
0135
0136 Example:
0137 nand@0 {
0138 partitions {
0139 compatible = "fixed-partitions";
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142
0143 preloader@0 {
0144 label = "pl";
0145 read-only;
0146 reg = <0x00000000 0x00400000>;
0147 };
0148 android@00400000 {
0149 label = "android";
0150 reg = <0x00400000 0x12c00000>;
0151 };
0152 };
0153 };
0154
0155 2) ECC Engine:
0156 ==============
0157
0158 Required BCH properties:
0159 - compatible: Should be one of
0160 "mediatek,mt2701-ecc",
0161 "mediatek,mt2712-ecc",
0162 "mediatek,mt7622-ecc".
0163 - reg: Base physical address and size of ECC.
0164 - interrupts: Interrupts of ECC.
0165 - clocks: ECC required clocks.
0166 - clock-names: ECC clocks internal name.
0167
0168 Example:
0169
0170 bch: ecc@1100e000 {
0171 compatible = "mediatek,mt2701-ecc";
0172 reg = <0 0x1100e000 0 0x1000>;
0173 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
0174 clocks = <&pericfg CLK_PERI_NFI_ECC>;
0175 clock-names = "nfiecc_clk";
0176 };
