0001 NXP LPC32xx SoC NAND MLC controller
0002
0003 Required properties:
0004 - compatible: "nxp,lpc3220-mlc"
0005 - reg: Address and size of the controller
0006 - interrupts: The NAND interrupt specification
0007 - gpios: GPIO specification for NAND write protect
0008
0009 The following required properties are very controller specific. See the LPC32xx
0010 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
0011 Hz, to make them independent of actual clock speed and to provide for good
0012 accuracy:)
0013 - nxp,tcea_delay: TCEA_DELAY
0014 - nxp,busy_delay: BUSY_DELAY
0015 - nxp,nand_ta: NAND_TA
0016 - nxp,rd_high: RD_HIGH
0017 - nxp,rd_low: RD_LOW
0018 - nxp,wr_high: WR_HIGH
0019 - nxp,wr_low: WR_LOW
0020
0021 Optional subnodes:
0022 - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
0023
0024 Example:
0025
0026 mlc: flash@200a8000 {
0027 compatible = "nxp,lpc3220-mlc";
0028 reg = <0x200A8000 0x11000>;
0029 interrupts = <11 0>;
0030 #address-cells = <1>;
0031 #size-cells = <1>;
0032
0033 nxp,tcea-delay = <333333333>;
0034 nxp,busy-delay = <10000000>;
0035 nxp,nand-ta = <18181818>;
0036 nxp,rd-high = <31250000>;
0037 nxp,rd-low = <45454545>;
0038 nxp,wr-high = <40000000>;
0039 nxp,wr-low = <83333333>;
0040 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
0041
0042 mtd0@00000000 {
0043 label = "boot";
0044 reg = <0x00000000 0x00064000>;
0045 read-only;
0046 };
0047
0048 ...
0049
0050 };
