0001 GPIO assisted NAND flash
0002
0003 The GPIO assisted NAND flash uses a memory mapped interface to
0004 read/write the NAND commands and data and GPIO pins for the control
0005 signals.
0006
0007 Required properties:
0008 - compatible : "gpio-control-nand"
0009 - reg : should specify localbus chip select and size used for the chip. The
0010 resource describes the data bus connected to the NAND flash and all accesses
0011 are made in native endianness.
0012 - #address-cells, #size-cells : Must be present if the device has sub-nodes
0013 representing partitions.
0014 - gpios : Specifies the GPIO pins to control the NAND device. The order of
0015 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
0016
0017 Optional properties:
0018 - bank-width : Width (in bytes) of the device. If not present, the width
0019 defaults to 1 byte.
0020 - chip-delay : chip dependent delay for transferring data from array to
0021 read registers (tR). If not present then a default of 20us is used.
0022 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
0023 location used to guard against bus reordering with regards to accesses to
0024 the GPIO's and the NAND flash data bus. If present, then after changing
0025 GPIO state and before and after command byte writes, this register will be
0026 read to ensure that the GPIO accesses have completed.
0027
0028 The device tree may optionally contain sub-nodes describing partitions of the
0029 address space. See partition.txt for more detail.
0030
0031 Examples:
0032
0033 gpio-nand@1,0 {
0034 compatible = "gpio-control-nand";
0035 reg = <1 0x0000 0x2>;
0036 #address-cells = <1>;
0037 #size-cells = <1>;
0038 gpios = <&banka 1 0>, /* RDY */
0039 <0>, /* nCE */
0040 <&banka 3 0>, /* ALE */
0041 <&banka 4 0>, /* CLE */
0042 <0>; /* nWP */
0043
0044 partition@0 {
0045 ...
0046 };
0047 };
