0001 ST Microelectronics Flexible Static Memory Controller (FSMC)
0002 NAND Interface
0003
0004 Required properties:
0005 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
0006 - reg : Address range of the mtd chip
0007 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
0008
0009 Optional properties:
0010 - bank-width : Width (in bytes) of the device. If not present, the width
0011 defaults to 1 byte
0012 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
0013 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
0014 are:
0015 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
0016 are valid. Zero means one clockcycle, 15 means 16 clock
0017 cycles.
0018 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
0019 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
0020 kept in Hi-Z (tristate) after the start of a write access.
0021 Only valid for write transactions. Zero means zero cycles,
0022 255 means 255 cycles.
0023 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
0024 when writing) after the command deassertation. Zero means
0025 one cycle, 255 means 256 cycles.
0026 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
0027 NAND flash in response to SMWAITn. Zero means 1 cycle,
0028 255 means 256 cycles.
0029 byte 5 TSET : number of HCLK clock cycles to assert the address before the
0030 command is asserted. Zero means one cycle, 255 means 256
0031 cycles.
0032 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
0033 - nand-ecc-mode : see nand-controller.yaml
0034 - nand-ecc-strength : see nand-controller.yaml
0035 - nand-ecc-step-size : see nand-controller.yaml
0036
0037 Can support 1-bit HW ECC (default) or if stronger correction is required,
0038 software-based BCH.
0039
0040 Example:
0041
0042 fsmc: flash@d1800000 {
0043 compatible = "st,spear600-fsmc-nand";
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 reg = <0xd1800000 0x1000 /* FSMC Register */
0047 0xd2000000 0x0010 /* NAND Base DATA */
0048 0xd2020000 0x0010 /* NAND Base ADDR */
0049 0xd2010000 0x0010>; /* NAND Base CMD */
0050 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
0051
0052 bank-width = <1>;
0053 nand-skip-bbtscan;
0054 timings = /bits/ 8 <0 0 0 2 3 0>;
0055 bank = <1>;
0056
0057 partition@0 {
0058 ...
0059 };
0060 };
