0001 * Cadence NAND controller
0002
0003 Required properties:
0004 - compatible : "cdns,hp-nfc"
0005 - reg : Contains two entries, each of which is a tuple consisting of a
0006 physical address and length. The first entry is the address and
0007 length of the controller register set. The second entry is the
0008 address and length of the Slave DMA data port.
0009 - reg-names: should contain "reg" and "sdma"
0010 - #address-cells: should be 1. The cell encodes the chip select connection.
0011 - #size-cells : should be 0.
0012 - interrupts : The interrupt number.
0013 - clocks: phandle of the controller core clock (nf_clk).
0014
0015 Optional properties:
0016 - dmas: shall reference DMA channel associated to the NAND controller
0017 - cdns,board-delay-ps : Estimated Board delay. The value includes the total
0018 round trip delay for the signals and is used for deciding on values
0019 associated with data read capture. The example formula for SDR mode is
0020 the following:
0021 board delay = RE#PAD delay + PCB trace to device + PCB trace from device
0022 + DQ PAD delay
0023
0024 Child nodes represent the available NAND chips.
0025
0026 Required properties of NAND chips:
0027 - reg: shall contain the native Chip Select ids from 0 to max supported by
0028 the cadence nand flash controller
0029
0030 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
0031 generic bindings.
0032
0033 Example:
0034
0035 nand_controller: nand-controller@60000000 {
0036 compatible = "cdns,hp-nfc";
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039 reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
0040 reg-names = "reg", "sdma";
0041 clocks = <&nf_clk>;
0042 cdns,board-delay-ps = <4830>;
0043 interrupts = <2 0>;
0044 nand@0 {
0045 reg = <0>;
0046 label = "nand-1";
0047 };
0048 nand@1 {
0049 reg = <1>;
0050 label = "nand-2";
0051 };
0052
0053 };
