0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom STB NAND Controller
0008
0009 maintainers:
0010 - Brian Norris <computersforpeace@gmail.com>
0011 - Kamal Dasu <kdasu.kdev@gmail.com>
0012
0013 description: |
0014 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
0015 flash chips. It has a memory-mapped register interface for both control
0016 registers and for its data input/output buffer. On some SoCs, this controller
0017 is paired with a custom DMA engine (inventively named "Flash DMA") which
0018 supports basic PROGRAM and READ functions, among other features.
0019
0020 This controller was originally designed for STB SoCs (BCM7xxx) but is now
0021 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
0022 iProc/Cygnus. Its history includes several similar (but not fully register
0023 compatible) versions.
0024
0025 -- Additional SoC-specific NAND controller properties --
0026
0027 The NAND controller is integrated differently on the variety of SoCs on which
0028 it is found. Part of this integration involves providing status and enable
0029 bits with which to control the 8 exposed NAND interrupts, as well as hardware
0030 for configuring the endianness of the data bus. On some SoCs, these features
0031 are handled via standard, modular components (e.g., their interrupts look like
0032 a normal IRQ chip), but on others, they are controlled in unique and
0033 interesting ways, sometimes with registers that lump multiple NAND-related
0034 functions together. The former case can be described simply by the standard
0035 interrupts properties in the main controller node. But for the latter
0036 exceptional cases, we define additional 'compatible' properties and associated
0037 register resources within the NAND controller node above.
0038
0039 properties:
0040 compatible:
0041 oneOf:
0042 - items:
0043 - enum:
0044 - brcm,brcmnand-v2.1
0045 - brcm,brcmnand-v2.2
0046 - brcm,brcmnand-v4.0
0047 - brcm,brcmnand-v5.0
0048 - brcm,brcmnand-v6.0
0049 - brcm,brcmnand-v6.1
0050 - brcm,brcmnand-v6.2
0051 - brcm,brcmnand-v7.0
0052 - brcm,brcmnand-v7.1
0053 - brcm,brcmnand-v7.2
0054 - brcm,brcmnand-v7.3
0055 - const: brcm,brcmnand
0056 - description: BCM63138 SoC-specific NAND controller
0057 items:
0058 - const: brcm,nand-bcm63138
0059 - enum:
0060 - brcm,brcmnand-v7.0
0061 - brcm,brcmnand-v7.1
0062 - const: brcm,brcmnand
0063 - description: iProc SoC-specific NAND controller
0064 items:
0065 - const: brcm,nand-iproc
0066 - const: brcm,brcmnand-v6.1
0067 - const: brcm,brcmnand
0068 - description: BCM63168 SoC-specific NAND controller
0069 items:
0070 - const: brcm,nand-bcm63168
0071 - const: brcm,nand-bcm6368
0072 - const: brcm,brcmnand-v4.0
0073 - const: brcm,brcmnand
0074
0075 reg:
0076 minItems: 1
0077 maxItems: 6
0078
0079 reg-names:
0080 minItems: 1
0081 maxItems: 6
0082 items:
0083 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
0084
0085 interrupts:
0086 minItems: 1
0087 items:
0088 - description: NAND CTLRDY interrupt
0089 - description: FLASH_DMA_DONE if flash DMA is available
0090 - description: FLASH_EDU_DONE if EDU is available
0091
0092 interrupt-names:
0093 minItems: 1
0094 items:
0095 - const: nand_ctlrdy
0096 - const: flash_dma_done
0097 - const: flash_edu_done
0098
0099 clocks:
0100 maxItems: 1
0101 description: reference to the clock for the NAND controller
0102
0103 clock-names:
0104 const: nand
0105
0106 brcm,nand-has-wp:
0107 description: >
0108 Some versions of this IP include a write-protect
0109 (WP) control bit. It is always available on >=
0110 v7.0. Use this property to describe the rare
0111 earlier versions of this core that include WP
0112 type: boolean
0113
0114 patternProperties:
0115 "^nand@[a-f0-9]$":
0116 type: object
0117 properties:
0118 compatible:
0119 const: brcm,nandcs
0120
0121 nand-ecc-step-size:
0122 enum: [ 512, 1024 ]
0123
0124 brcm,nand-oob-sector-size:
0125 description: |
0126 integer, to denote the spare area sector size
0127 expected for the ECC layout in use. This size, in
0128 addition to the strength and step-size,
0129 determines how the hardware BCH engine will lay
0130 out the parity bytes it stores on the flash.
0131 This property can be automatically determined by
0132 the flash geometry (particularly the NAND page
0133 and OOB size) in many cases, but when booting
0134 from NAND, the boot controller has only a limited
0135 number of available options for its default ECC
0136 layout.
0137 $ref: /schemas/types.yaml#/definitions/uint32
0138
0139 allOf:
0140 - $ref: nand-controller.yaml#
0141 - if:
0142 properties:
0143 compatible:
0144 contains:
0145 const: brcm,nand-bcm63138
0146 then:
0147 properties:
0148 reg-names:
0149 items:
0150 - const: nand
0151 - const: nand-int-base
0152 - if:
0153 properties:
0154 compatible:
0155 contains:
0156 const: brcm,nand-bcm6368
0157 then:
0158 properties:
0159 reg-names:
0160 items:
0161 - const: nand
0162 - const: nand-int-base
0163 - const: nand-cache
0164 - if:
0165 properties:
0166 compatible:
0167 contains:
0168 const: brcm,nand-iproc
0169 then:
0170 properties:
0171 reg-names:
0172 items:
0173 - const: nand
0174 - const: iproc-idm
0175 - const: iproc-ext
0176
0177 unevaluatedProperties: false
0178
0179 required:
0180 - reg
0181 - reg-names
0182 - interrupts
0183
0184 examples:
0185 - |
0186 nand-controller@f0442800 {
0187 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
0188 reg = <0xf0442800 0x600>,
0189 <0xf0443000 0x100>;
0190 reg-names = "nand", "flash-dma";
0191 interrupt-parent = <&hif_intr2_intc>;
0192 interrupts = <24>, <4>;
0193
0194 #address-cells = <1>;
0195 #size-cells = <0>;
0196
0197 nand@1 {
0198 compatible = "brcm,nandcs";
0199 reg = <1>; // Chip select 1
0200 nand-on-flash-bbt;
0201 nand-ecc-strength = <12>;
0202 nand-ecc-step-size = <512>;
0203
0204 #address-cells = <1>;
0205 #size-cells = <1>;
0206 };
0207 };
0208 - |
0209 nand-controller@10000200 {
0210 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
0211 "brcm,brcmnand-v4.0", "brcm,brcmnand";
0212 reg = <0x10000200 0x180>,
0213 <0x100000b0 0x10>,
0214 <0x10000600 0x200>;
0215 reg-names = "nand", "nand-int-base", "nand-cache";
0216 interrupt-parent = <&periph_intc>;
0217 interrupts = <50>;
0218 clocks = <&periph_clk 20>;
0219 clock-names = "nand";
0220
0221 #address-cells = <1>;
0222 #size-cells = <0>;
0223
0224 nand@0 {
0225 compatible = "brcm,nandcs";
0226 reg = <0>;
0227 nand-on-flash-bbt;
0228 nand-ecc-strength = <1>;
0229 nand-ecc-step-size = <512>;
0230
0231 #address-cells = <1>;
0232 #size-cells = <1>;
0233 };
0234 };
