0001 Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
0002
0003 This file documents the properties in addition to those available in
0004 the MTD NAND bindings.
0005
0006 Required properties:
0007 - compatible : contains one of:
0008 - "amlogic,meson-gxl-nfc"
0009 - "amlogic,meson-axg-nfc"
0010 - clocks :
0011 A list of phandle + clock-specifier pairs for the clocks listed
0012 in clock-names.
0013
0014 - clock-names: Should contain the following:
0015 "core" - NFC module gate clock
0016 "device" - device clock from eMMC sub clock controller
0017 "rx" - rx clock phase
0018 "tx" - tx clock phase
0019
0020 - amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
0021 controller port C
0022
0023 Optional children nodes:
0024 Children nodes represent the available nand chips.
0025
0026 Other properties:
0027 see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
0028
0029 Example demonstrate on AXG SoC:
0030
0031 sd_emmc_c_clkc: mmc@7000 {
0032 compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
0033 reg = <0x0 0x7000 0x0 0x800>;
0034 };
0035
0036 nand-controller@7800 {
0037 compatible = "amlogic,meson-axg-nfc";
0038 reg = <0x0 0x7800 0x0 0x100>;
0039 #address-cells = <1>;
0040 #size-cells = <0>;
0041 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
0042
0043 clocks = <&clkc CLKID_SD_EMMC_C>,
0044 <&sd_emmc_c_clkc CLKID_MMC_DIV>,
0045 <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
0046 <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
0047 clock-names = "core", "device", "rx", "tx";
0048 amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
0049
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&nand_pins>;
0052
0053 nand@0 {
0054 reg = <0>;
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057
0058 nand-on-flash-bbt;
0059 };
0060 };
