0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Synopsys Designware Mobile Storage Host Controller Binding
0008
0009 allOf:
0010 - $ref: "synopsys-dw-mshc-common.yaml#"
0011
0012 maintainers:
0013 - Ulf Hansson <ulf.hansson@linaro.org>
0014
0015 # Everything else is described in the common file
0016 properties:
0017 compatible:
0018 enum:
0019 - altr,socfpga-dw-mshc
0020 - img,pistachio-dw-mshc
0021 - snps,dw-mshc
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 minItems: 2
0031 maxItems: 2
0032 description:
0033 Handle to "biu" and "ciu" clocks for the
0034 bus interface unit clock and the card interface unit clock.
0035
0036 clock-names:
0037 items:
0038 - const: biu
0039 - const: ciu
0040
0041 required:
0042 - compatible
0043 - reg
0044 - interrupts
0045 - clocks
0046 - clock-names
0047
0048 unevaluatedProperties: false
0049
0050 examples:
0051 - |
0052 mmc@12200000 {
0053 compatible = "snps,dw-mshc";
0054 reg = <0x12200000 0x1000>;
0055 interrupts = <0 75 0>;
0056 clocks = <&clock 351>, <&clock 132>;
0057 clock-names = "biu", "ciu";
0058 dmas = <&pdma 12>;
0059 dma-names = "rx-tx";
0060 resets = <&rst 20>;
0061 reset-names = "reset";
0062 vmmc-supply = <&buck8>;
0063 #address-cells = <1>;
0064 #size-cells = <0>;
0065 broken-cd;
0066 bus-width = <8>;
0067 cap-mmc-highspeed;
0068 cap-sd-highspeed;
0069 card-detect-delay = <200>;
0070 max-frequency = <200000000>;
0071 clock-frequency = <400000000>;
0072 data-addr = <0x200>;
0073 fifo-depth = <0x80>;
0074 fifo-watermark-aligned;
0075 };
