0001 * Spreadtrum SDHCI controller (sdhci-sprd)
0002
0003 The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
0004 for MMC, SD and SDIO types of cards.
0005
0006 This file documents differences between the core properties in mmc.txt
0007 and the properties used by the sdhci-sprd driver.
0008
0009 Required properties:
0010 - compatible: Should contain "sprd,sdhci-r11".
0011 - reg: physical base address of the controller and length.
0012 - interrupts: Interrupts used by the SDHCI controller.
0013 - clocks: Should contain phandle for the clock feeding the SDHCI controller
0014 - clock-names: Should contain the following:
0015 "sdio" - SDIO source clock (required)
0016 "enable" - gate clock which used for enabling/disabling the device (required)
0017 "2x_enable" - gate clock controlling the device for some special platforms (optional)
0018
0019 Optional properties:
0020 - assigned-clocks: the same with "sdio" clock
0021 - assigned-clock-parents: the default parent of "sdio" clock
0022 - pinctrl-names: should be "default", "state_uhs"
0023 - pinctrl-0: should contain default/high speed pin control
0024 - pinctrl-1: should contain uhs mode pin control
0025
0026 PHY DLL delays are used to delay the data valid window, and align the window
0027 to sampling clock. PHY DLL delays can be configured by following properties,
0028 and each property contains 4 cells which are used to configure the clock data
0029 write line delay value, clock read command line delay value, clock read data
0030 positive edge delay value and clock read data negative edge delay value.
0031 Each cell's delay value unit is cycle of the PHY clock.
0032
0033 - sprd,phy-delay-legacy: Delay value for legacy timing.
0034 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
0035 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
0036 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
0037 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
0038 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
0039 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
0040 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
0041 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
0042
0043 Examples:
0044
0045 sdio0: sdio@20600000 {
0046 compatible = "sprd,sdhci-r11";
0047 reg = <0 0x20600000 0 0x1000>;
0048 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0049
0050 clock-names = "sdio", "enable";
0051 clocks = <&ap_clk CLK_EMMC_2X>,
0052 <&apahb_gate CLK_EMMC_EB>;
0053 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
0054 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
0055
0056 pinctrl-names = "default", "state_uhs";
0057 pinctrl-0 = <&sd0_pins_default>;
0058 pinctrl-1 = <&sd0_pins_uhs>;
0059
0060 sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
0061 bus-width = <8>;
0062 non-removable;
0063 no-sdio;
0064 no-sd;
0065 cap-mmc-hw-reset;
0066 status = "okay";
0067 };
