0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Qualcomm SDHCI controller (sdhci-msm)
0009
0010 maintainers:
0011 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
0012
0013 description:
0014 Secure Digital Host Controller Interface (SDHCI) present on
0015 Qualcomm SOCs supports SD/MMC/SDIO devices.
0016
0017 properties:
0018 compatible:
0019 oneOf:
0020 - enum:
0021 - qcom,sdhci-msm-v4
0022 deprecated: true
0023 - items:
0024 - enum:
0025 - qcom,apq8084-sdhci
0026 - qcom,msm8226-sdhci
0027 - qcom,msm8953-sdhci
0028 - qcom,msm8974-sdhci
0029 - qcom,msm8916-sdhci
0030 - qcom,msm8992-sdhci
0031 - qcom,msm8994-sdhci
0032 - qcom,msm8996-sdhci
0033 - qcom,msm8998-sdhci
0034 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
0035 - items:
0036 - enum:
0037 - qcom,qcs404-sdhci
0038 - qcom,sc7180-sdhci
0039 - qcom,sc7280-sdhci
0040 - qcom,sdm630-sdhci
0041 - qcom,sdm845-sdhci
0042 - qcom,sdx55-sdhci
0043 - qcom,sdx65-sdhci
0044 - qcom,sm6125-sdhci
0045 - qcom,sm6350-sdhci
0046 - qcom,sm8150-sdhci
0047 - qcom,sm8250-sdhci
0048 - qcom,sm8450-sdhci
0049 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
0050
0051 reg:
0052 minItems: 1
0053 maxItems: 4
0054
0055 reg-names:
0056 minItems: 1
0057 maxItems: 4
0058
0059 clocks:
0060 minItems: 3
0061 items:
0062 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
0063 - description: SDC MMC clock, MCLK
0064 - description: TCXO clock
0065 - description: clock for Inline Crypto Engine
0066 - description: SDCC bus voter clock
0067 - description: reference clock for RCLK delay calibration
0068 - description: sleep clock for RCLK delay calibration
0069
0070 clock-names:
0071 minItems: 2
0072 items:
0073 - const: iface
0074 - const: core
0075 - const: xo
0076 - const: ice
0077 - const: bus
0078 - const: cal
0079 - const: sleep
0080
0081 interrupts:
0082 maxItems: 2
0083
0084 interrupt-names:
0085 items:
0086 - const: hc_irq
0087 - const: pwr_irq
0088
0089 pinctrl-names:
0090 minItems: 1
0091 items:
0092 - const: default
0093 - const: sleep
0094
0095 pinctrl-0:
0096 description:
0097 Should specify pin control groups used for this controller.
0098
0099 resets:
0100 maxItems: 1
0101
0102 qcom,ddr-config:
0103 $ref: /schemas/types.yaml#/definitions/uint32
0104 description: platform specific settings for DDR_CONFIG reg.
0105
0106 qcom,dll-config:
0107 $ref: /schemas/types.yaml#/definitions/uint32
0108 description: platform specific settings for DLL_CONFIG reg.
0109
0110 iommus:
0111 minItems: 1
0112 maxItems: 8
0113 description: |
0114 phandle to apps_smmu node with sid mask.
0115
0116 interconnects:
0117 items:
0118 - description: data path, sdhc to ddr
0119 - description: config path, cpu to sdhc
0120
0121 interconnect-names:
0122 items:
0123 - const: sdhc-ddr
0124 - const: cpu-sdhc
0125
0126 power-domains:
0127 description: A phandle to sdhci power domain node
0128 maxItems: 1
0129
0130 mmc-ddr-1_8v: true
0131
0132 mmc-hs200-1_8v: true
0133
0134 mmc-hs400-1_8v: true
0135
0136 bus-width: true
0137
0138 max-frequency: true
0139
0140 operating-points-v2: true
0141
0142 patternProperties:
0143 '^opp-table(-[a-z0-9]+)?$':
0144 if:
0145 properties:
0146 compatible:
0147 const: operating-points-v2
0148 then:
0149 patternProperties:
0150 '^opp-?[0-9]+$':
0151 required:
0152 - required-opps
0153
0154 required:
0155 - compatible
0156 - reg
0157 - clocks
0158 - clock-names
0159 - interrupts
0160
0161 allOf:
0162 - $ref: mmc-controller.yaml#
0163
0164 - if:
0165 properties:
0166 compatible:
0167 contains:
0168 enum:
0169 - qcom,sdhci-msm-v4
0170 then:
0171 properties:
0172 reg:
0173 minItems: 2
0174 items:
0175 - description: Host controller register map
0176 - description: SD Core register map
0177 - description: CQE register map
0178 - description: Inline Crypto Engine register map
0179 reg-names:
0180 minItems: 2
0181 items:
0182 - const: hc
0183 - const: core
0184 - const: cqhci
0185 - const: ice
0186 else:
0187 properties:
0188 reg:
0189 minItems: 1
0190 items:
0191 - description: Host controller register map
0192 - description: CQE register map
0193 - description: Inline Crypto Engine register map
0194 reg-names:
0195 minItems: 1
0196 items:
0197 - const: hc
0198 - const: cqhci
0199 - const: ice
0200
0201 unevaluatedProperties: false
0202
0203 examples:
0204 - |
0205 #include <dt-bindings/interrupt-controller/arm-gic.h>
0206 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
0207 #include <dt-bindings/clock/qcom,rpmh.h>
0208 #include <dt-bindings/power/qcom-rpmpd.h>
0209
0210 sdhc_2: mmc@8804000 {
0211 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
0212 reg = <0 0x08804000 0 0x1000>;
0213
0214 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
0216 interrupt-names = "hc_irq", "pwr_irq";
0217
0218 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
0219 <&gcc GCC_SDCC2_APPS_CLK>,
0220 <&rpmhcc RPMH_CXO_CLK>;
0221 clock-names = "iface", "core", "xo";
0222 iommus = <&apps_smmu 0x4a0 0x0>;
0223 qcom,dll-config = <0x0007642c>;
0224 qcom,ddr-config = <0x80040868>;
0225 power-domains = <&rpmhpd SM8250_CX>;
0226
0227 operating-points-v2 = <&sdhc2_opp_table>;
0228
0229 sdhc2_opp_table: opp-table {
0230 compatible = "operating-points-v2";
0231
0232 opp-19200000 {
0233 opp-hz = /bits/ 64 <19200000>;
0234 required-opps = <&rpmhpd_opp_min_svs>;
0235 };
0236
0237 opp-50000000 {
0238 opp-hz = /bits/ 64 <50000000>;
0239 required-opps = <&rpmhpd_opp_low_svs>;
0240 };
0241
0242 opp-100000000 {
0243 opp-hz = /bits/ 64 <100000000>;
0244 required-opps = <&rpmhpd_opp_svs>;
0245 };
0246
0247 opp-202000000 {
0248 opp-hz = /bits/ 64 <202000000>;
0249 required-opps = <&rpmhpd_opp_svs_l1>;
0250 };
0251 };
0252 };
