0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: TI AM654 MMC Controller
0009
0010 maintainers:
0011 - Ulf Hansson <ulf.hansson@linaro.org>
0012
0013 allOf:
0014 - $ref: mmc-controller.yaml#
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - const: ti,am654-sdhci-5.1
0020 - const: ti,j721e-sdhci-8bit
0021 - const: ti,j721e-sdhci-4bit
0022 - const: ti,am64-sdhci-8bit
0023 - const: ti,am64-sdhci-4bit
0024 - const: ti,am62-sdhci
0025 - items:
0026 - const: ti,j7200-sdhci-8bit
0027 - const: ti,j721e-sdhci-8bit
0028 - items:
0029 - const: ti,j7200-sdhci-4bit
0030 - const: ti,j721e-sdhci-4bit
0031
0032 reg:
0033 maxItems: 2
0034
0035 interrupts:
0036 maxItems: 1
0037
0038 power-domains:
0039 maxItems: 1
0040
0041 clocks:
0042 minItems: 1
0043 maxItems: 2
0044 description: Handles to input clocks
0045
0046 clock-names:
0047 minItems: 1
0048 items:
0049 - const: clk_ahb
0050 - const: clk_xin
0051
0052 sdhci-caps-mask: true
0053
0054 # PHY output tap delays:
0055 # Used to delay the data valid window and align it to the sampling clock.
0056 # Binding needs to be provided for each supported speed mode otherwise the
0057 # corresponding mode will be disabled.
0058
0059 ti,otap-del-sel-legacy:
0060 description: Output tap delay for SD/MMC legacy timing
0061 $ref: "/schemas/types.yaml#/definitions/uint32"
0062 minimum: 0
0063 maximum: 0xf
0064
0065 ti,otap-del-sel-mmc-hs:
0066 description: Output tap delay for MMC high speed timing
0067 $ref: "/schemas/types.yaml#/definitions/uint32"
0068 minimum: 0
0069 maximum: 0xf
0070
0071 ti,otap-del-sel-sd-hs:
0072 description: Output tap delay for SD high speed timing
0073 $ref: "/schemas/types.yaml#/definitions/uint32"
0074 minimum: 0
0075 maximum: 0xf
0076
0077 ti,otap-del-sel-sdr12:
0078 description: Output tap delay for SD UHS SDR12 timing
0079 $ref: "/schemas/types.yaml#/definitions/uint32"
0080 minimum: 0
0081 maximum: 0xf
0082
0083 ti,otap-del-sel-sdr25:
0084 description: Output tap delay for SD UHS SDR25 timing
0085 $ref: "/schemas/types.yaml#/definitions/uint32"
0086 minimum: 0
0087 maximum: 0xf
0088
0089 ti,otap-del-sel-sdr50:
0090 description: Output tap delay for SD UHS SDR50 timing
0091 $ref: "/schemas/types.yaml#/definitions/uint32"
0092 minimum: 0
0093 maximum: 0xf
0094
0095 ti,otap-del-sel-sdr104:
0096 description: Output tap delay for SD UHS SDR104 timing
0097 $ref: "/schemas/types.yaml#/definitions/uint32"
0098 minimum: 0
0099 maximum: 0xf
0100
0101 ti,otap-del-sel-ddr50:
0102 description: Output tap delay for SD UHS DDR50 timing
0103 $ref: "/schemas/types.yaml#/definitions/uint32"
0104 minimum: 0
0105 maximum: 0xf
0106
0107 ti,otap-del-sel-ddr52:
0108 description: Output tap delay for eMMC DDR52 timing
0109 $ref: "/schemas/types.yaml#/definitions/uint32"
0110 minimum: 0
0111 maximum: 0xf
0112
0113 ti,otap-del-sel-hs200:
0114 description: Output tap delay for eMMC HS200 timing
0115 $ref: "/schemas/types.yaml#/definitions/uint32"
0116 minimum: 0
0117 maximum: 0xf
0118
0119 ti,otap-del-sel-hs400:
0120 description: Output tap delay for eMMC HS400 timing
0121 $ref: "/schemas/types.yaml#/definitions/uint32"
0122 minimum: 0
0123 maximum: 0xf
0124
0125 # PHY input tap delays:
0126 # Used to delay the data valid window and align it to the sampling clock for
0127 # modes that don't support tuning
0128
0129 ti,itap-del-sel-legacy:
0130 description: Input tap delay for SD/MMC legacy timing
0131 $ref: "/schemas/types.yaml#/definitions/uint32"
0132 minimum: 0
0133 maximum: 0x1f
0134
0135 ti,itap-del-sel-mmc-hs:
0136 description: Input tap delay for MMC high speed timing
0137 $ref: "/schemas/types.yaml#/definitions/uint32"
0138 minimum: 0
0139 maximum: 0x1f
0140
0141 ti,itap-del-sel-sd-hs:
0142 description: Input tap delay for SD high speed timing
0143 $ref: "/schemas/types.yaml#/definitions/uint32"
0144 minimum: 0
0145 maximum: 0x1f
0146
0147 ti,itap-del-sel-sdr12:
0148 description: Input tap delay for SD UHS SDR12 timing
0149 $ref: "/schemas/types.yaml#/definitions/uint32"
0150 minimum: 0
0151 maximum: 0x1f
0152
0153 ti,itap-del-sel-sdr25:
0154 description: Input tap delay for SD UHS SDR25 timing
0155 $ref: "/schemas/types.yaml#/definitions/uint32"
0156 minimum: 0
0157 maximum: 0x1f
0158
0159 ti,itap-del-sel-ddr52:
0160 description: Input tap delay for MMC DDR52 timing
0161 $ref: "/schemas/types.yaml#/definitions/uint32"
0162 minimum: 0
0163 maximum: 0x1f
0164
0165 ti,trm-icp:
0166 description: DLL trim select
0167 $ref: "/schemas/types.yaml#/definitions/uint32"
0168 minimum: 0
0169 maximum: 0xf
0170
0171 ti,driver-strength-ohm:
0172 description: DLL drive strength in ohms
0173 $ref: "/schemas/types.yaml#/definitions/uint32"
0174 enum:
0175 - 33
0176 - 40
0177 - 50
0178 - 66
0179 - 100
0180
0181 ti,strobe-sel:
0182 description: strobe select delay for HS400 speed mode.
0183 $ref: "/schemas/types.yaml#/definitions/uint32"
0184
0185 ti,clkbuf-sel:
0186 description: Clock Delay Buffer Select
0187 $ref: "/schemas/types.yaml#/definitions/uint32"
0188
0189 ti,fails-without-test-cd:
0190 $ref: /schemas/types.yaml#/definitions/flag
0191 description:
0192 When present, indicates that the CD line is not connected
0193 and the controller is required to be forced into Test mode
0194 to set the TESTCD bit.
0195
0196 required:
0197 - compatible
0198 - reg
0199 - interrupts
0200 - clocks
0201 - clock-names
0202 - ti,otap-del-sel-legacy
0203
0204 unevaluatedProperties: false
0205
0206 examples:
0207 - |
0208 #include <dt-bindings/interrupt-controller/irq.h>
0209 #include <dt-bindings/interrupt-controller/arm-gic.h>
0210
0211 bus {
0212 #address-cells = <2>;
0213 #size-cells = <2>;
0214
0215 mmc0: mmc@4f80000 {
0216 compatible = "ti,am654-sdhci-5.1";
0217 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
0218 power-domains = <&k3_pds 47>;
0219 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
0220 clock-names = "clk_ahb", "clk_xin";
0221 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0222 sdhci-caps-mask = <0x80000007 0x0>;
0223 mmc-ddr-1_8v;
0224 ti,otap-del-sel-legacy = <0x0>;
0225 ti,otap-del-sel-mmc-hs = <0x0>;
0226 ti,otap-del-sel-ddr52 = <0x5>;
0227 ti,otap-del-sel-hs200 = <0x5>;
0228 ti,otap-del-sel-hs400 = <0x0>;
0229 ti,itap-del-sel-legacy = <0x10>;
0230 ti,itap-del-sel-mmc-hs = <0xa>;
0231 ti,itap-del-sel-ddr52 = <0x3>;
0232 ti,trm-icp = <0x8>;
0233 };
0234 };
