0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title:
0008 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
0009 Storage Host Controller
0010
0011 maintainers:
0012 - Jaehoon Chung <jh80.chung@samsung.com>
0013 - Krzysztof Kozlowski <krzk@kernel.org>
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - samsung,exynos4210-dw-mshc
0019 - samsung,exynos4412-dw-mshc
0020 - samsung,exynos5250-dw-mshc
0021 - samsung,exynos5420-dw-mshc
0022 - samsung,exynos5420-dw-mshc-smu
0023 - samsung,exynos7-dw-mshc
0024 - samsung,exynos7-dw-mshc-smu
0025 - axis,artpec8-dw-mshc
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 clocks:
0034 maxItems: 2
0035 description:
0036 Handle to "biu" and "ciu" clocks for the
0037 bus interface unit clock and the card interface unit clock.
0038
0039 clock-names:
0040 items:
0041 - const: biu
0042 - const: ciu
0043
0044 samsung,dw-mshc-ciu-div:
0045 $ref: /schemas/types.yaml#/definitions/uint32
0046 minimum: 0
0047 maximum: 7
0048 description:
0049 The divider value for the card interface unit (ciu) clock.
0050
0051 samsung,dw-mshc-ddr-timing:
0052 $ref: /schemas/types.yaml#/definitions/uint32-array
0053 items:
0054 - description: CIU clock phase shift value for tx mode
0055 minimum: 0
0056 maximum: 7
0057 - description: CIU clock phase shift value for rx mode
0058 minimum: 0
0059 maximum: 7
0060 description:
0061 The value of CUI clock phase shift value in transmit mode and CIU clock
0062 phase shift value in receive mode for double data rate mode operation.
0063 See also samsung,dw-mshc-hs400-timing property.
0064
0065 samsung,dw-mshc-hs400-timing:
0066 $ref: /schemas/types.yaml#/definitions/uint32-array
0067 items:
0068 - description: CIU clock phase shift value for tx mode
0069 minimum: 0
0070 maximum: 7
0071 - description: CIU clock phase shift value for rx mode
0072 minimum: 0
0073 maximum: 7
0074 description: |
0075 The value of CIU TX and RX clock phase shift value for HS400 mode
0076 operation.
0077 Valid values for SDR and DDR CIU clock timing::
0078 - valid value for tx phase shift and rx phase shift is 0 to 7.
0079 - when CIU clock divider value is set to 3, all possible 8 phase shift
0080 values can be used.
0081 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
0082 phase shift clocks should be 0.
0083 If missing, values from samsung,dw-mshc-ddr-timing property are used.
0084
0085 samsung,dw-mshc-sdr-timing:
0086 $ref: /schemas/types.yaml#/definitions/uint32-array
0087 items:
0088 - description: CIU clock phase shift value for tx mode
0089 minimum: 0
0090 maximum: 7
0091 - description: CIU clock phase shift value for rx mode
0092 minimum: 0
0093 maximum: 7
0094 description:
0095 The value of CIU clock phase shift value in transmit mode and CIU clock
0096 phase shift value in receive mode for single data rate mode operation.
0097 See also samsung,dw-mshc-hs400-timing property.
0098
0099 samsung,read-strobe-delay:
0100 $ref: /schemas/types.yaml#/definitions/uint32
0101 description:
0102 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
0103 line in Read path). If missing, default from hardware is used.
0104
0105 required:
0106 - compatible
0107 - reg
0108 - interrupts
0109 - clocks
0110 - clock-names
0111 - samsung,dw-mshc-ddr-timing
0112 - samsung,dw-mshc-sdr-timing
0113
0114 allOf:
0115 - $ref: "synopsys-dw-mshc-common.yaml#"
0116 - if:
0117 properties:
0118 compatible:
0119 contains:
0120 enum:
0121 - samsung,exynos5250-dw-mshc
0122 - samsung,exynos5420-dw-mshc
0123 - samsung,exynos7-dw-mshc
0124 - samsung,exynos7-dw-mshc-smu
0125 - axis,artpec8-dw-mshc
0126 then:
0127 required:
0128 - samsung,dw-mshc-ciu-div
0129
0130 unevaluatedProperties: false
0131
0132 examples:
0133 - |
0134 #include <dt-bindings/clock/exynos5420.h>
0135 #include <dt-bindings/interrupt-controller/arm-gic.h>
0136
0137 mmc@12220000 {
0138 compatible = "samsung,exynos5420-dw-mshc";
0139 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0140 #address-cells = <1>;
0141 #size-cells = <0>;
0142 reg = <0x12220000 0x1000>;
0143 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0144 clock-names = "biu", "ciu";
0145 fifo-depth = <0x40>;
0146 card-detect-delay = <200>;
0147 samsung,dw-mshc-ciu-div = <3>;
0148 samsung,dw-mshc-sdr-timing = <0 4>;
0149 samsung,dw-mshc-ddr-timing = <0 2>;
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
0152 bus-width = <4>;
0153 cap-sd-highspeed;
0154 max-frequency = <200000000>;
0155 vmmc-supply = <&ldo19_reg>;
0156 vqmmc-supply = <&ldo13_reg>;
0157 sd-uhs-sdr50;
0158 sd-uhs-sdr104;
0159 sd-uhs-ddr50;
0160 };
