0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Secure Digital Host Controller
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 This controller on Tegra family SoCs provides an interface for MMC, SD, and
0015 SDIO types of memory cards.
0016
0017 This file documents differences between the core properties described by
0018 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
0019
0020 properties:
0021 compatible:
0022 oneOf:
0023 - enum:
0024 - nvidia,tegra20-sdhci
0025 - nvidia,tegra30-sdhci
0026 - nvidia,tegra114-sdhci
0027 - nvidia,tegra124-sdhci
0028 - nvidia,tegra210-sdhci
0029 - nvidia,tegra186-sdhci
0030 - nvidia,tegra194-sdhci
0031
0032 - items:
0033 - const: nvidia,tegra132-sdhci
0034 - const: nvidia,tegra124-sdhci
0035
0036 - items:
0037 - enum:
0038 - nvidia,tegra194-sdhci
0039 - nvidia,tegra234-sdhci
0040 - const: nvidia,tegra186-sdhci
0041
0042 reg:
0043 maxItems: 1
0044
0045 interrupts:
0046 maxItems: 1
0047
0048 assigned-clocks: true
0049 assigned-clock-parents: true
0050 assigned-clock-rates: true
0051
0052 clocks:
0053 minItems: 1
0054 maxItems: 2
0055
0056 clock-names:
0057 minItems: 1
0058 maxItems: 2
0059
0060 resets:
0061 items:
0062 - description: module reset
0063
0064 reset-names:
0065 items:
0066 - const: sdhci
0067
0068 power-gpios:
0069 description: specify GPIOs for power control
0070 maxItems: 1
0071
0072 interconnects:
0073 items:
0074 - description: memory read client
0075 - description: memory write client
0076
0077 interconnect-names:
0078 items:
0079 - const: dma-mem # read
0080 - const: write
0081
0082 iommus:
0083 maxItems: 1
0084
0085 operating-points-v2:
0086 $ref: "/schemas/types.yaml#/definitions/phandle"
0087
0088 power-domains:
0089 items:
0090 - description: phandle to the core power domain
0091
0092 nvidia,default-tap:
0093 description: Specify the default inbound sampling clock trimmer value for
0094 non-tunable modes.
0095
0096 The values are used for compensating trace length differences by
0097 adjusting the sampling point. The values are programmed to the Vendor
0098 Clock Control Register. Please refer to the reference manual of the SoC
0099 for correct values.
0100
0101 The DQS trim values are only used on controllers which support HS400
0102 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
0103 $ref: "/schemas/types.yaml#/definitions/uint32"
0104
0105 nvidia,default-trim:
0106 description: Specify the default outbound clock trimmer value.
0107 $ref: "/schemas/types.yaml#/definitions/uint32"
0108
0109 nvidia,dqs-trim:
0110 description: Specify DQS trim value for HS400 timing.
0111 $ref: "/schemas/types.yaml#/definitions/uint32"
0112
0113 nvidia,pad-autocal-pull-down-offset-1v8:
0114 description: Specify drive strength calibration offsets for 1.8 V
0115 signaling modes.
0116 $ref: "/schemas/types.yaml#/definitions/uint32"
0117
0118 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
0119 description: Specify drive strength used as a fallback in case the
0120 automatic calibration times out on a 1.8 V signaling mode.
0121 $ref: "/schemas/types.yaml#/definitions/uint32"
0122
0123 nvidia,pad-autocal-pull-down-offset-3v3:
0124 description: Specify drive strength calibration offsets for 3.3 V
0125 signaling modes.
0126 $ref: "/schemas/types.yaml#/definitions/uint32"
0127
0128 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
0129 description: Specify drive strength used as a fallback in case the
0130 automatic calibration times out on a 3.3 V signaling mode.
0131 $ref: "/schemas/types.yaml#/definitions/uint32"
0132
0133 nvidia,pad-autocal-pull-down-offset-sdr104:
0134 description: Specify drive strength calibration offsets for SDR104 mode.
0135 $ref: "/schemas/types.yaml#/definitions/uint32"
0136
0137 nvidia,pad-autocal-pull-down-offset-hs400:
0138 description: Specify drive strength calibration offsets for HS400 mode.
0139 $ref: "/schemas/types.yaml#/definitions/uint32"
0140
0141 nvidia,pad-autocal-pull-up-offset-1v8:
0142 description: Specify drive strength calibration offsets for 1.8 V
0143 signaling modes.
0144 $ref: "/schemas/types.yaml#/definitions/uint32"
0145
0146 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
0147 description: Specify drive strength used as a fallback in case the
0148 automatic calibration times out on a 1.8 V signaling mode.
0149 $ref: "/schemas/types.yaml#/definitions/uint32"
0150
0151 nvidia,pad-autocal-pull-up-offset-3v3:
0152 description: Specify drive strength calibration offsets for 3.3 V
0153 signaling modes.
0154
0155 The property values are drive codes which are programmed into the
0156 PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
0157 register. A higher value corresponds to higher drive strength. Please
0158 refer to the reference manual of the SoC for correct values. The SDR104
0159 and HS400 timing specific values are used in corresponding modes if
0160 specified.
0161 $ref: "/schemas/types.yaml#/definitions/uint32"
0162
0163 nvidia,pad-autocal-pull-up-offset-3v3-timeout:
0164 description: Specify drive strength used as a fallback in case the
0165 automatic calibration times out on a 3.3 V signaling mode.
0166 $ref: "/schemas/types.yaml#/definitions/uint32"
0167
0168 nvidia,pad-autocal-pull-up-offset-sdr104:
0169 description: Specify drive strength calibration offsets for SDR104 mode.
0170 $ref: "/schemas/types.yaml#/definitions/uint32"
0171
0172 nvidia,pad-autocal-pull-up-offset-hs400:
0173 description: Specify drive strength calibration offsets for HS400 mode.
0174 $ref: "/schemas/types.yaml#/definitions/uint32"
0175
0176 nvidia,only-1-8v:
0177 description: The presence of this property indicates that the controller
0178 operates at a 1.8 V fixed I/O voltage.
0179 $ref: "/schemas/types.yaml#/definitions/flag"
0180
0181 required:
0182 - compatible
0183 - reg
0184 - interrupts
0185 - clocks
0186 - resets
0187 - reset-names
0188
0189 allOf:
0190 - $ref: "mmc-controller.yaml"
0191 - if:
0192 properties:
0193 compatible:
0194 contains:
0195 enum:
0196 - nvidia,tegra20-sdhci
0197 - nvidia,tegra30-sdhci
0198 - nvidia,tegra114-sdhci
0199 - nvidia,tegra124-sdhci
0200 then:
0201 properties:
0202 clocks:
0203 items:
0204 - description: module clock
0205 else:
0206 properties:
0207 clocks:
0208 items:
0209 - description: module clock
0210 - description: timeout clock
0211
0212 clock-names:
0213 items:
0214 - const: sdhci
0215 - const: tmclk
0216 required:
0217 - clock-names
0218
0219 - if:
0220 properties:
0221 compatible:
0222 contains:
0223 const: nvidia,tegra210-sdhci
0224 then:
0225 properties:
0226 pinctrl-names:
0227 oneOf:
0228 - items:
0229 - const: sdmmc-3v3
0230 description: pad configuration for 3.3 V
0231 - const: sdmmc-1v8
0232 description: pad configuration for 1.8 V
0233 - const: sdmmc-3v3-drv
0234 description: pull-up/down configuration for 3.3 V
0235 - const: sdmmc-1v8-drv
0236 description: pull-up/down configuration for 1.8 V
0237 - items:
0238 - const: sdmmc-3v3-drv
0239 description: pull-up/down configuration for 3.3 V
0240 - const: sdmmc-1v8-drv
0241 description: pull-up/down configuration for 1.8 V
0242 - items:
0243 - const: sdmmc-1v8-drv
0244 description: pull-up/down configuration for 1.8 V
0245 required:
0246 - clock-names
0247 - if:
0248 properties:
0249 compatible:
0250 contains:
0251 enum:
0252 - nvidia,tegra186-sdhci
0253 - nvidia,tegra194-sdhci
0254 then:
0255 properties:
0256 pinctrl-names:
0257 items:
0258 - const: sdmmc-3v3
0259 description: pad configuration for 3.3 V
0260 - const: sdmmc-1v8
0261 description: pad configuration for 1.8 V
0262 required:
0263 - clock-names
0264
0265 unevaluatedProperties: false
0266
0267 examples:
0268 - |
0269 #include <dt-bindings/interrupt-controller/arm-gic.h>
0270
0271 mmc@c8000200 {
0272 compatible = "nvidia,tegra20-sdhci";
0273 reg = <0xc8000200 0x200>;
0274 interrupts = <47>;
0275 clocks = <&tegra_car 14>;
0276 resets = <&tegra_car 14>;
0277 reset-names = "sdhci";
0278 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
0279 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
0280 power-gpios = <&gpio 155 0>; /* gpio PT3 */
0281 bus-width = <8>;
0282 };
0283
0284 - |
0285 #include <dt-bindings/clock/tegra210-car.h>
0286 #include <dt-bindings/interrupt-controller/arm-gic.h>
0287
0288 mmc@700b0000 {
0289 compatible = "nvidia,tegra210-sdhci";
0290 reg = <0x700b0000 0x200>;
0291 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0292 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
0293 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
0294 clock-names = "sdhci", "tmclk";
0295 resets = <&tegra_car 14>;
0296 reset-names = "sdhci";
0297 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
0298 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
0299 pinctrl-0 = <&sdmmc1_3v3>;
0300 pinctrl-1 = <&sdmmc1_1v8>;
0301 pinctrl-2 = <&sdmmc1_3v3_drv>;
0302 pinctrl-3 = <&sdmmc1_1v8_drv>;
0303 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
0304 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
0305 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
0306 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
0307 nvidia,default-tap = <0x2>;
0308 nvidia,default-trim = <0x4>;
0309 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
0310 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
0311 <&tegra_car TEGRA210_CLK_PLL_C4>;
0312 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
0313 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
0314 };
