0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MTK MSDC Storage Host Controller Binding
0008
0009 maintainers:
0010 - Chaotian Jing <chaotian.jing@mediatek.com>
0011 - Wenbin Mei <wenbin.mei@mediatek.com>
0012
0013 allOf:
0014 - $ref: mmc-controller.yaml#
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - enum:
0020 - mediatek,mt2701-mmc
0021 - mediatek,mt2712-mmc
0022 - mediatek,mt6779-mmc
0023 - mediatek,mt7620-mmc
0024 - mediatek,mt7622-mmc
0025 - mediatek,mt8135-mmc
0026 - mediatek,mt8173-mmc
0027 - mediatek,mt8183-mmc
0028 - mediatek,mt8516-mmc
0029 - items:
0030 - const: mediatek,mt7623-mmc
0031 - const: mediatek,mt2701-mmc
0032 - items:
0033 - enum:
0034 - mediatek,mt8186-mmc
0035 - mediatek,mt8188-mmc
0036 - mediatek,mt8192-mmc
0037 - mediatek,mt8195-mmc
0038 - const: mediatek,mt8183-mmc
0039
0040 reg:
0041 minItems: 1
0042 items:
0043 - description: base register (required).
0044 - description: top base register (required for MT8183).
0045
0046 clocks:
0047 description:
0048 Should contain phandle for the clock feeding the MMC controller.
0049 minItems: 2
0050 items:
0051 - description: source clock (required).
0052 - description: HCLK which used for host (required).
0053 - description: independent source clock gate (required for MT2712).
0054 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
0055 - description: msdc subsys clock gate (required for MT8192).
0056 - description: peripheral bus clock gate (required for MT8192).
0057 - description: AXI bus clock gate (required for MT8192).
0058 - description: AHB bus clock gate (required for MT8192).
0059
0060 clock-names:
0061 minItems: 2
0062 items:
0063 - const: source
0064 - const: hclk
0065 - const: source_cg
0066 - const: bus_clk
0067 - const: sys_cg
0068 - const: pclk_cg
0069 - const: axi_cg
0070 - const: ahb_cg
0071
0072 interrupts:
0073 description:
0074 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
0075 interrupt is required and be configured as wakeup source irq.
0076 minItems: 1
0077 maxItems: 2
0078
0079 interrupt-names:
0080 items:
0081 - const: msdc
0082 - const: sdio_wakeup
0083
0084 pinctrl-names:
0085 description:
0086 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
0087 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
0088 scenario.
0089 minItems: 2
0090 items:
0091 - const: default
0092 - const: state_uhs
0093 - const: state_eint
0094
0095 pinctrl-0:
0096 description:
0097 should contain default/high speed pin ctrl.
0098 maxItems: 1
0099
0100 pinctrl-1:
0101 description:
0102 should contain uhs mode pin ctrl.
0103 maxItems: 1
0104
0105 pinctrl-2:
0106 description:
0107 should switch dat1 pin to GPIO mode.
0108 maxItems: 1
0109
0110 assigned-clocks:
0111 description:
0112 PLL of the source clock.
0113 maxItems: 1
0114
0115 assigned-clock-parents:
0116 description:
0117 parent of source clock, used for HS400 mode to get 400Mhz source clock.
0118 maxItems: 1
0119
0120 hs400-ds-delay:
0121 $ref: /schemas/types.yaml#/definitions/uint32
0122 description:
0123 HS400 DS delay setting.
0124 minimum: 0
0125 maximum: 0xffffffff
0126
0127 mediatek,hs200-cmd-int-delay:
0128 $ref: /schemas/types.yaml#/definitions/uint32
0129 description:
0130 HS200 command internal delay setting.
0131 This field has total 32 stages.
0132 The value is an integer from 0 to 31.
0133 minimum: 0
0134 maximum: 31
0135
0136 mediatek,hs400-cmd-int-delay:
0137 $ref: /schemas/types.yaml#/definitions/uint32
0138 description:
0139 HS400 command internal delay setting.
0140 This field has total 32 stages.
0141 The value is an integer from 0 to 31.
0142 minimum: 0
0143 maximum: 31
0144
0145 mediatek,hs400-cmd-resp-sel-rising:
0146 $ref: /schemas/types.yaml#/definitions/flag
0147 description:
0148 HS400 command response sample selection.
0149 If present, HS400 command responses are sampled on rising edges.
0150 If not present, HS400 command responses are sampled on falling edges.
0151
0152 mediatek,hs400-ds-dly3:
0153 $ref: /schemas/types.yaml#/definitions/uint32
0154 description:
0155 Gear of the third delay line for DS for input data latch in data
0156 pad macro, there are 32 stages from 0 to 31.
0157 For different corner IC, the time is different about one step, it is
0158 about 100ps.
0159 The value is confirmed by doing scan and calibration to find a best
0160 value with corner IC and it is valid only for HS400 mode.
0161 minimum: 0
0162 maximum: 31
0163
0164 mediatek,latch-ck:
0165 $ref: /schemas/types.yaml#/definitions/uint32
0166 description:
0167 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
0168 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
0169 if not present, default value is 0.
0170 applied to compatible "mediatek,mt2701-mmc".
0171 minimum: 0
0172 maximum: 7
0173
0174 resets:
0175 maxItems: 1
0176
0177 reset-names:
0178 const: hrst
0179
0180 required:
0181 - compatible
0182 - reg
0183 - interrupts
0184 - clocks
0185 - clock-names
0186 - pinctrl-names
0187 - pinctrl-0
0188 - pinctrl-1
0189 - vmmc-supply
0190 - vqmmc-supply
0191
0192 if:
0193 properties:
0194 compatible:
0195 contains:
0196 const: mediatek,mt8183-mmc
0197 then:
0198 properties:
0199 reg:
0200 minItems: 2
0201
0202 unevaluatedProperties: false
0203
0204 examples:
0205 - |
0206 #include <dt-bindings/interrupt-controller/irq.h>
0207 #include <dt-bindings/interrupt-controller/arm-gic.h>
0208 #include <dt-bindings/clock/mt8173-clk.h>
0209 mmc0: mmc@11230000 {
0210 compatible = "mediatek,mt8173-mmc";
0211 reg = <0x11230000 0x1000>;
0212 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
0213 vmmc-supply = <&mt6397_vemc_3v3_reg>;
0214 vqmmc-supply = <&mt6397_vio18_reg>;
0215 clocks = <&pericfg CLK_PERI_MSDC30_0>,
0216 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
0217 clock-names = "source", "hclk";
0218 pinctrl-names = "default", "state_uhs";
0219 pinctrl-0 = <&mmc0_pins_default>;
0220 pinctrl-1 = <&mmc0_pins_uhs>;
0221 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
0222 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
0223 hs400-ds-delay = <0x14015>;
0224 mediatek,hs200-cmd-int-delay = <26>;
0225 mediatek,hs400-cmd-int-delay = <14>;
0226 mediatek,hs400-cmd-resp-sel-rising;
0227 };
0228
0229 mmc3: mmc@11260000 {
0230 compatible = "mediatek,mt8173-mmc";
0231 reg = <0x11260000 0x1000>;
0232 clock-names = "source", "hclk";
0233 clocks = <&pericfg CLK_PERI_MSDC30_3>,
0234 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
0235 interrupt-names = "msdc", "sdio_wakeup";
0236 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
0237 <&pio 23 IRQ_TYPE_LEVEL_LOW>;
0238 pinctrl-names = "default", "state_uhs", "state_eint";
0239 pinctrl-0 = <&mmc2_pins_default>;
0240 pinctrl-1 = <&mmc2_pins_uhs>;
0241 pinctrl-2 = <&mmc2_pins_eint>;
0242 bus-width = <4>;
0243 max-frequency = <200000000>;
0244 cap-sd-highspeed;
0245 sd-uhs-sdr104;
0246 keep-power-in-suspend;
0247 wakeup-source;
0248 cap-sdio-irq;
0249 no-mmc;
0250 no-sd;
0251 non-removable;
0252 vmmc-supply = <&sdio_fixed_3v3>;
0253 vqmmc-supply = <&mt6397_vgp3_reg>;
0254 mmc-pwrseq = <&wifi_pwrseq>;
0255 };
0256
0257 ...
