0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Marvell Xenon SDHCI Controller
0008
0009 description: |
0010 This file documents differences between the core MMC properties described by
0011 mmc-controller.yaml and the properties used by the Xenon implementation.
0012
0013 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
0014 Each SDHC is independent and owns independent resources, such as register
0015 sets, clock and PHY.
0016
0017 Each SDHC should have an independent device tree node.
0018
0019 maintainers:
0020 - Ulf Hansson <ulf.hansson@linaro.org>
0021
0022 properties:
0023 compatible:
0024 oneOf:
0025 - enum:
0026 - marvell,armada-cp110-sdhci
0027 - marvell,armada-ap806-sdhci
0028
0029 - items:
0030 - const: marvell,armada-ap807-sdhci
0031 - const: marvell,armada-ap806-sdhci
0032
0033 - items:
0034 - const: marvell,armada-3700-sdhci
0035 - const: marvell,sdhci-xenon
0036
0037 reg:
0038 minItems: 1
0039 maxItems: 2
0040 description: |
0041 For "marvell,armada-3700-sdhci", two register areas. The first one
0042 for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
0043 Voltage Control register. Please follow the examples with compatible
0044 "marvell,armada-3700-sdhci" in below.
0045 Please also check property marvell,pad-type in below.
0046
0047 For other compatible strings, one register area for Xenon IP.
0048
0049 clocks:
0050 minItems: 1
0051 maxItems: 2
0052
0053 clock-names:
0054 minItems: 1
0055 items:
0056 - const: core
0057 - const: axi
0058
0059 interrupts:
0060 maxItems: 1
0061
0062 marvell,xenon-sdhc-id:
0063 $ref: /schemas/types.yaml#/definitions/uint32
0064 minimum: 0
0065 maximum: 7
0066 description: |
0067 Indicate the corresponding bit index of current SDHC in SDHC System
0068 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
0069 enable/disable current SDHC.
0070
0071 marvell,xenon-phy-type:
0072 $ref: /schemas/types.yaml#/definitions/string
0073 enum:
0074 - "emmc 5.1 phy"
0075 - "emmc 5.0 phy"
0076 description: |
0077 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
0078 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
0079 choice if this property is not provided. To select eMMC 5.0 PHY, set:
0080 marvell,xenon-phy-type = "emmc 5.0 phy"
0081
0082 All those types of PHYs can support eMMC, SD and SDIO. Please note that
0083 this property only presents the type of PHY. It doesn't stand for the
0084 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
0085 that this Xenon SDHC only supports eMMC 5.1.
0086
0087 marvell,xenon-phy-znr:
0088 $ref: /schemas/types.yaml#/definitions/uint32
0089 minimum: 0
0090 maximum: 0x1f
0091 default: 0xf
0092 description: |
0093 Set PHY ZNR value.
0094 Only available for eMMC PHY.
0095
0096 marvell,xenon-phy-zpr:
0097 $ref: /schemas/types.yaml#/definitions/uint32
0098 minimum: 0
0099 maximum: 0x1f
0100 default: 0xf
0101 description: |
0102 Set PHY ZPR value.
0103 Only available for eMMC PHY.
0104
0105 marvell,xenon-phy-nr-success-tun:
0106 $ref: /schemas/types.yaml#/definitions/uint32
0107 minimum: 1
0108 maximum: 7
0109 default: 0x4
0110 description: |
0111 Set the number of required consecutive successful sampling points
0112 used to identify a valid sampling window, in tuning process.
0113
0114 marvell,xenon-phy-tun-step-divider:
0115 $ref: /schemas/types.yaml#/definitions/uint32
0116 default: 64
0117 description: |
0118 Set the divider for calculating TUN_STEP.
0119
0120 marvell,xenon-phy-slow-mode:
0121 type: boolean
0122 description: |
0123 If this property is selected, transfers will bypass PHY.
0124 Only available when bus frequency lower than 55MHz in SDR mode.
0125 Disabled by default. Please only try this property if timing issues
0126 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
0127 SD Default Speed and HS mode and eMMC legacy speed mode.
0128
0129 marvell,xenon-tun-count:
0130 $ref: /schemas/types.yaml#/definitions/uint32
0131 default: 0x9
0132 description: |
0133 Xenon SDHC SoC usually doesn't provide re-tuning counter in
0134 Capabilities Register 3 Bit[11:8].
0135 This property provides the re-tuning counter.
0136
0137 allOf:
0138 - $ref: mmc-controller.yaml#
0139 - if:
0140 properties:
0141 compatible:
0142 contains:
0143 const: marvell,armada-3700-sdhci
0144
0145 then:
0146 properties:
0147 reg:
0148 items:
0149 - description: Xenon IP registers
0150 - description: Armada 3700 SoC PHY PAD Voltage Control register
0151
0152 marvell,pad-type:
0153 $ref: /schemas/types.yaml#/definitions/string
0154 enum:
0155 - sd
0156 - fixed-1-8v
0157 description: |
0158 Type of Armada 3700 SoC PHY PAD Voltage Controller register.
0159 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
0160 and is switched to 1.8V when later in higher speed mode.
0161 If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
0162 eMMC.
0163 Please follow the examples with compatible
0164 "marvell,armada-3700-sdhci" in below.
0165
0166 required:
0167 - marvell,pad-type
0168
0169 - if:
0170 properties:
0171 compatible:
0172 contains:
0173 enum:
0174 - marvell,armada-cp110-sdhci
0175 - marvell,armada-ap807-sdhci
0176 - marvell,armada-ap806-sdhci
0177
0178 then:
0179 properties:
0180 clocks:
0181 minItems: 2
0182
0183 clock-names:
0184 items:
0185 - const: core
0186 - const: axi
0187
0188
0189 required:
0190 - compatible
0191 - reg
0192 - clocks
0193 - clock-names
0194
0195 unevaluatedProperties: false
0196
0197 examples:
0198 - |
0199 // For eMMC
0200 #include <dt-bindings/interrupt-controller/arm-gic.h>
0201 #include <dt-bindings/interrupt-controller/irq.h>
0202
0203 mmc@aa0000 {
0204 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
0205 reg = <0xaa0000 0x1000>;
0206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&emmc_clk 0>, <&axi_clk 0>;
0208 clock-names = "core", "axi";
0209 bus-width = <4>;
0210 marvell,xenon-phy-slow-mode;
0211 marvell,xenon-tun-count = <11>;
0212 non-removable;
0213 no-sd;
0214 no-sdio;
0215
0216 /* Vmmc and Vqmmc are both fixed */
0217 };
0218
0219 - |
0220 // For SD/SDIO
0221 #include <dt-bindings/interrupt-controller/arm-gic.h>
0222 #include <dt-bindings/interrupt-controller/irq.h>
0223
0224 mmc@ab0000 {
0225 compatible = "marvell,armada-cp110-sdhci";
0226 reg = <0xab0000 0x1000>;
0227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0228 vqmmc-supply = <&sd_vqmmc_regulator>;
0229 vmmc-supply = <&sd_vmmc_regulator>;
0230 clocks = <&sdclk 0>, <&axi_clk 0>;
0231 clock-names = "core", "axi";
0232 bus-width = <4>;
0233 marvell,xenon-tun-count = <9>;
0234 };
0235
0236 - |
0237 // For eMMC with compatible "marvell,armada-3700-sdhci":
0238 #include <dt-bindings/interrupt-controller/arm-gic.h>
0239 #include <dt-bindings/interrupt-controller/irq.h>
0240
0241 mmc@aa0000 {
0242 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
0243 reg = <0xaa0000 0x1000>,
0244 <0x17808 0x4>;
0245 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0246 clocks = <&emmcclk 0>;
0247 clock-names = "core";
0248 bus-width = <8>;
0249 mmc-ddr-1_8v;
0250 mmc-hs400-1_8v;
0251 non-removable;
0252 no-sd;
0253 no-sdio;
0254
0255 /* Vmmc and Vqmmc are both fixed */
0256
0257 marvell,pad-type = "fixed-1-8v";
0258 };
0259
0260 - |
0261 // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
0262 #include <dt-bindings/interrupt-controller/arm-gic.h>
0263 #include <dt-bindings/interrupt-controller/irq.h>
0264
0265 mmc@ab0000 {
0266 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
0267 reg = <0xab0000 0x1000>,
0268 <0x17808 0x4>;
0269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0270 vqmmc-supply = <&sd_regulator>;
0271 /* Vmmc is fixed */
0272 clocks = <&sdclk 0>;
0273 clock-names = "core";
0274 bus-width = <4>;
0275
0276 marvell,pad-type = "sd";
0277 };
