0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
0008
0009 maintainers:
0010 - Masahiro Yamada <yamada.masahiro@socionext.com>
0011 - Piotr Sroka <piotrs@cadence.com>
0012
0013 allOf:
0014 - $ref: mmc-controller.yaml
0015
0016 properties:
0017 compatible:
0018 items:
0019 - enum:
0020 - microchip,mpfs-sd4hc
0021 - socionext,uniphier-sd4hc
0022 - const: cdns,sd4hc
0023
0024 reg:
0025 maxItems: 1
0026
0027 interrupts:
0028 maxItems: 1
0029
0030 clocks:
0031 maxItems: 1
0032
0033 # PHY DLL input delays:
0034 # They are used to delay the data valid window, and align the window to
0035 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
0036 # and it is increased by 2.5ns in each step.
0037
0038 cdns,phy-input-delay-sd-highspeed:
0039 description: Value of the delay in the input path for SD high-speed timing
0040 $ref: "/schemas/types.yaml#/definitions/uint32"
0041 minimum: 0
0042 maximum: 0x1f
0043
0044 cdns,phy-input-delay-legacy:
0045 description: Value of the delay in the input path for legacy timing
0046 $ref: "/schemas/types.yaml#/definitions/uint32"
0047 minimum: 0
0048 maximum: 0x1f
0049
0050 cdns,phy-input-delay-sd-uhs-sdr12:
0051 description: Value of the delay in the input path for SD UHS SDR12 timing
0052 $ref: "/schemas/types.yaml#/definitions/uint32"
0053 minimum: 0
0054 maximum: 0x1f
0055
0056 cdns,phy-input-delay-sd-uhs-sdr25:
0057 description: Value of the delay in the input path for SD UHS SDR25 timing
0058 $ref: "/schemas/types.yaml#/definitions/uint32"
0059 minimum: 0
0060 maximum: 0x1f
0061
0062 cdns,phy-input-delay-sd-uhs-sdr50:
0063 description: Value of the delay in the input path for SD UHS SDR50 timing
0064 $ref: "/schemas/types.yaml#/definitions/uint32"
0065 minimum: 0
0066 maximum: 0x1f
0067
0068 cdns,phy-input-delay-sd-uhs-ddr50:
0069 description: Value of the delay in the input path for SD UHS DDR50 timing
0070 $ref: "/schemas/types.yaml#/definitions/uint32"
0071 minimum: 0
0072 maximum: 0x1f
0073
0074 cdns,phy-input-delay-mmc-highspeed:
0075 description: Value of the delay in the input path for MMC high-speed timing
0076 $ref: "/schemas/types.yaml#/definitions/uint32"
0077 minimum: 0
0078 maximum: 0x1f
0079
0080 cdns,phy-input-delay-mmc-ddr:
0081 description: Value of the delay in the input path for eMMC high-speed DDR timing
0082
0083 # PHY DLL clock delays:
0084 # Each delay property represents the fraction of the clock period.
0085 # The approximate delay value will be
0086 # (<delay property value>/128)*sdmclk_clock_period.
0087 $ref: "/schemas/types.yaml#/definitions/uint32"
0088 minimum: 0
0089 maximum: 0x1f
0090
0091 cdns,phy-dll-delay-sdclk:
0092 description: |
0093 Value of the delay introduced on the sdclk output for all modes except
0094 HS200, HS400 and HS400_ES.
0095 $ref: "/schemas/types.yaml#/definitions/uint32"
0096 minimum: 0
0097 maximum: 0x7f
0098
0099 cdns,phy-dll-delay-sdclk-hsmmc:
0100 description: |
0101 Value of the delay introduced on the sdclk output for HS200, HS400 and
0102 HS400_ES speed modes.
0103 $ref: "/schemas/types.yaml#/definitions/uint32"
0104 minimum: 0
0105 maximum: 0x7f
0106
0107 cdns,phy-dll-delay-strobe:
0108 description: |
0109 Value of the delay introduced on the dat_strobe input used in
0110 HS400 / HS400_ES speed modes.
0111 $ref: "/schemas/types.yaml#/definitions/uint32"
0112 minimum: 0
0113 maximum: 0x7f
0114
0115 required:
0116 - compatible
0117 - reg
0118 - interrupts
0119 - clocks
0120
0121 unevaluatedProperties: false
0122
0123 examples:
0124 - |
0125 emmc: mmc@5a000000 {
0126 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
0127 reg = <0x5a000000 0x400>;
0128 interrupts = <0 78 4>;
0129 clocks = <&clk 4>;
0130 bus-width = <8>;
0131 mmc-ddr-1_8v;
0132 mmc-hs200-1_8v;
0133 mmc-hs400-1_8v;
0134 cdns,phy-dll-delay-sdclk = <0>;
0135 };
