0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
0008
0009 maintainers:
0010 - Linus Walleij <linus.walleij@linaro.org>
0011 - Ulf Hansson <ulf.hansson@linaro.org>
0012
0013 description:
0014 The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
0015 reading and writing to MultiMedia and SD cards alike. Over the years
0016 vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
0017 host controllers with very similar characteristics.
0018
0019 allOf:
0020 - $ref: /schemas/arm/primecell.yaml#
0021 - $ref: mmc-controller.yaml#
0022
0023 # We need a select here so we don't match all nodes with 'arm,primecell'
0024 select:
0025 properties:
0026 compatible:
0027 contains:
0028 enum:
0029 - arm,pl180
0030 - arm,pl181
0031 - arm,pl18x
0032 required:
0033 - compatible
0034
0035 properties:
0036 compatible:
0037 oneOf:
0038 - description: The first version of the block, simply called
0039 PL180 and found in the ARM Integrator IM/PD1 logic module.
0040 items:
0041 - const: arm,pl180
0042 - const: arm,primecell
0043 - description: The improved version of the block, found in the
0044 ARM Versatile and later reference designs. Further revisions
0045 exist but get detected at runtime by reading some magic numbers
0046 in the PrimeCell ID registers.
0047 items:
0048 - const: arm,pl181
0049 - const: arm,primecell
0050 - description: Wildcard entry that will let the operating system
0051 inspect the PrimeCell ID registers to determine which hardware
0052 variant of PL180 or PL181 this is.
0053 items:
0054 - const: arm,pl18x
0055 - const: arm,primecell
0056 - description: Entry for STMicroelectronics variant of PL18x.
0057 This dedicated compatible is used by bootloaders.
0058 items:
0059 - const: st,stm32-sdmmc2
0060 - const: arm,pl18x
0061 - const: arm,primecell
0062
0063 clocks:
0064 description: One or two clocks, the "apb_pclk" and the "MCLK"
0065 which is the core block clock. The names are not compulsory.
0066 minItems: 1
0067 maxItems: 2
0068
0069 dmas:
0070 maxItems: 2
0071
0072 dma-names:
0073 oneOf:
0074 - items:
0075 - const: tx
0076 - const: rx
0077 - items:
0078 - const: rx
0079 - const: tx
0080
0081 power-domains: true
0082
0083 resets:
0084 maxItems: 1
0085
0086 reg:
0087 description: the MMIO memory window must be exactly 4KB (0x1000) and the
0088 layout should provide the PrimeCell ID registers so that the device can
0089 be discovered. On ST Micro variants, a second register window may be
0090 defined if a delay block is present and used for tuning.
0091
0092 interrupts:
0093 description: The first interrupt is the command interrupt and corresponds
0094 to the event at the end of a command. The second interrupt is the
0095 PIO (polled I/O) interrupt and occurs when the FIFO needs to be
0096 emptied as part of a bulk read from the card. Some variants have these
0097 two interrupts wired into the same line (logic OR) and in that case
0098 only one interrupt may be provided.
0099 minItems: 1
0100 maxItems: 2
0101
0102 st,sig-dir-dat0:
0103 $ref: /schemas/types.yaml#/definitions/flag
0104 description: ST Micro-specific property, bus signal direction pins used for
0105 DAT[0].
0106
0107 st,sig-dir-dat2:
0108 $ref: /schemas/types.yaml#/definitions/flag
0109 description: ST Micro-specific property, bus signal direction pins used for
0110 DAT[2].
0111
0112 st,sig-dir-dat31:
0113 $ref: /schemas/types.yaml#/definitions/flag
0114 description: ST Micro-specific property, bus signal direction pins used for
0115 DAT[3] and DAT[1].
0116
0117 st,sig-dir-dat74:
0118 $ref: /schemas/types.yaml#/definitions/flag
0119 description: ST Micro-specific property, bus signal direction pins used for
0120 DAT[7] and DAT[4].
0121
0122 st,sig-dir-cmd:
0123 $ref: /schemas/types.yaml#/definitions/flag
0124 description: ST Micro-specific property, CMD signal direction used for
0125 pin CMD.
0126
0127 st,sig-pin-fbclk:
0128 $ref: /schemas/types.yaml#/definitions/flag
0129 description: ST Micro-specific property, feedback clock FBCLK signal pin
0130 in use.
0131
0132 st,sig-dir:
0133 $ref: /schemas/types.yaml#/definitions/flag
0134 description: ST Micro-specific property, signal direction polarity used for
0135 pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
0136
0137 st,neg-edge:
0138 $ref: /schemas/types.yaml#/definitions/flag
0139 description: ST Micro-specific property, data and command phase relation,
0140 generated on the sd clock falling edge.
0141
0142 st,use-ckin:
0143 $ref: /schemas/types.yaml#/definitions/flag
0144 description: ST Micro-specific property, use CKIN pin from an external
0145 driver to sample the receive data (for example with a voltage switch
0146 transceiver).
0147
0148 st,cmd-gpios:
0149 maxItems: 1
0150 description:
0151 The GPIO matching the CMD pin.
0152
0153 st,ck-gpios:
0154 maxItems: 1
0155 description:
0156 The GPIO matching the CK pin.
0157
0158 st,ckin-gpios:
0159 maxItems: 1
0160 description:
0161 The GPIO matching the CKIN pin.
0162
0163 dependencies:
0164 st,cmd-gpios: [ "st,use-ckin" ]
0165 st,ck-gpios: [ "st,use-ckin" ]
0166 st,ckin-gpios: [ "st,use-ckin" ]
0167
0168 unevaluatedProperties: false
0169
0170 required:
0171 - compatible
0172 - reg
0173 - interrupts
0174
0175 examples:
0176 - |
0177 #include <dt-bindings/interrupt-controller/irq.h>
0178 #include <dt-bindings/gpio/gpio.h>
0179
0180 mmc@5000 {
0181 compatible = "arm,pl180", "arm,primecell";
0182 reg = <0x5000 0x1000>;
0183 interrupts-extended = <&vic 22 &sic 1>;
0184 clocks = <&xtal24mhz>, <&pclk>;
0185 clock-names = "mclk", "apb_pclk";
0186 };
0187
0188 - |
0189 #include <dt-bindings/interrupt-controller/irq.h>
0190
0191 mmc@80126000 {
0192 compatible = "arm,pl18x", "arm,primecell";
0193 reg = <0x80126000 0x1000>;
0194 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
0195 dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
0196 dma-names = "rx", "tx";
0197 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
0198 clock-names = "sdi", "apb_pclk";
0199 max-frequency = <100000000>;
0200 bus-width = <4>;
0201 cap-sd-highspeed;
0202 cap-mmc-highspeed;
0203 cd-gpios = <&gpio2 31 0x4>;
0204 st,sig-dir-dat0;
0205 st,sig-dir-dat2;
0206 st,sig-dir-cmd;
0207 st,sig-pin-fbclk;
0208 vmmc-supply = <&ab8500_ldo_aux3_reg>;
0209 vqmmc-supply = <&vmmci>;
0210 };
0211
0212 - |
0213 mmc@101f6000 {
0214 compatible = "arm,pl18x", "arm,primecell";
0215 reg = <0x101f6000 0x1000>;
0216 clocks = <&sdiclk>, <&pclksdi>;
0217 clock-names = "mclk", "apb_pclk";
0218 interrupts = <22>;
0219 max-frequency = <400000>;
0220 bus-width = <4>;
0221 cap-mmc-highspeed;
0222 cap-sd-highspeed;
0223 full-pwr-cycle;
0224 st,sig-dir-dat0;
0225 st,sig-dir-dat2;
0226 st,sig-dir-dat31;
0227 st,sig-dir-cmd;
0228 st,sig-pin-fbclk;
0229 vmmc-supply = <&vmmc_regulator>;
0230 };
0231
0232 - |
0233 mmc@52007000 {
0234 compatible = "arm,pl18x", "arm,primecell";
0235 arm,primecell-periphid = <0x10153180>;
0236 reg = <0x52007000 0x1000>;
0237 interrupts = <49>;
0238 clocks = <&rcc 0>;
0239 clock-names = "apb_pclk";
0240 resets = <&rcc 1>;
0241 cap-sd-highspeed;
0242 cap-mmc-highspeed;
0243 max-frequency = <120000000>;
0244 };
