0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Device Tree Bindings for the Arasan SDHCI Controller
0008
0009 maintainers:
0010 - Adrian Hunter <adrian.hunter@intel.com>
0011
0012 allOf:
0013 - $ref: "mmc-controller.yaml#"
0014 - if:
0015 properties:
0016 compatible:
0017 contains:
0018 const: arasan,sdhci-5.1
0019 then:
0020 required:
0021 - phys
0022 - phy-names
0023 - if:
0024 properties:
0025 compatible:
0026 contains:
0027 enum:
0028 - xlnx,zynqmp-8.9a
0029 - xlnx,versal-8.9a
0030 then:
0031 properties:
0032 clock-output-names:
0033 oneOf:
0034 - items:
0035 - const: clk_out_sd0
0036 - const: clk_in_sd0
0037 - items:
0038 - const: clk_out_sd1
0039 - const: clk_in_sd1
0040
0041 properties:
0042 compatible:
0043 oneOf:
0044 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
0045 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
0046 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
0047 - items:
0048 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
0049 - const: arasan,sdhci-5.1
0050 description:
0051 For this device it is strongly suggested to include
0052 arasan,soc-ctl-syscon.
0053 - items:
0054 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
0055 - const: arasan,sdhci-8.9a
0056 description:
0057 For this device it is strongly suggested to include
0058 clock-output-names and '#clock-cells'.
0059 - items:
0060 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
0061 - const: arasan,sdhci-8.9a
0062 description:
0063 For this device it is strongly suggested to include
0064 clock-output-names and '#clock-cells'.
0065 - items:
0066 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
0067 - const: arasan,sdhci-5.1
0068 description:
0069 For this device it is strongly suggested to include
0070 arasan,soc-ctl-syscon.
0071 - items:
0072 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
0073 - const: arasan,sdhci-5.1
0074 description:
0075 For this device it is strongly suggested to include
0076 arasan,soc-ctl-syscon.
0077 - items:
0078 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
0079 - const: arasan,sdhci-5.1
0080 description:
0081 For this device it is strongly suggested to include
0082 arasan,soc-ctl-syscon.
0083 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
0084 description:
0085 For this device it is strongly suggested to include
0086 arasan,soc-ctl-syscon.
0087 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
0088 description:
0089 For this device it is strongly suggested to include
0090 arasan,soc-ctl-syscon.
0091 - items:
0092 - const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
0093 - const: arasan,sdhci-5.1
0094 description:
0095 For this device it is strongly suggested to include
0096 clock-output-names and '#clock-cells'.
0097
0098 reg:
0099 maxItems: 1
0100
0101 clocks:
0102 minItems: 2
0103 maxItems: 3
0104
0105 clock-names:
0106 minItems: 2
0107 items:
0108 - const: clk_xin
0109 - const: clk_ahb
0110 - const: gate
0111
0112 interrupts:
0113 maxItems: 1
0114
0115 phys:
0116 maxItems: 1
0117
0118 phy-names:
0119 const: phy_arasan
0120
0121 resets:
0122 maxItems: 1
0123
0124 arasan,soc-ctl-syscon:
0125 $ref: /schemas/types.yaml#/definitions/phandle
0126 description:
0127 A phandle to a syscon device (see ../mfd/syscon.txt) used to access
0128 core corecfg registers. Offsets of registers in this syscon are
0129 determined based on the main compatible string for the device.
0130
0131 clock-output-names:
0132 minItems: 1
0133 maxItems: 2
0134 description:
0135 Name of the card clock which will be exposed by this device.
0136
0137 '#clock-cells':
0138 enum: [0, 1]
0139 description:
0140 With this property in place we will export one or two clocks
0141 representing the Card Clock. These clocks are expected to be
0142 consumed by our PHY.
0143
0144 xlnx,fails-without-test-cd:
0145 $ref: /schemas/types.yaml#/definitions/flag
0146 description:
0147 When present, the controller doesn't work when the CD line is not
0148 connected properly, and the line is not connected properly.
0149 Test mode can be used to force the controller to function.
0150
0151 xlnx,int-clock-stable-broken:
0152 $ref: /schemas/types.yaml#/definitions/flag
0153 description:
0154 When present, the controller always reports that the internal clock
0155 is stable even when it is not.
0156
0157 xlnx,mio-bank:
0158 $ref: /schemas/types.yaml#/definitions/uint32
0159 enum: [0, 1, 2]
0160 default: 0
0161 description:
0162 The MIO bank number in which the command and data lines are configured.
0163
0164 dependencies:
0165 '#clock-cells': [ clock-output-names ]
0166
0167 required:
0168 - compatible
0169 - reg
0170 - interrupts
0171 - clocks
0172 - clock-names
0173
0174 unevaluatedProperties: false
0175
0176 examples:
0177 - |
0178 mmc@e0100000 {
0179 compatible = "arasan,sdhci-8.9a";
0180 reg = <0xe0100000 0x1000>;
0181 clock-names = "clk_xin", "clk_ahb";
0182 clocks = <&clkc 21>, <&clkc 32>;
0183 interrupt-parent = <&gic>;
0184 interrupts = <0 24 4>;
0185 };
0186
0187 - |
0188 mmc@e2800000 {
0189 compatible = "arasan,sdhci-5.1";
0190 reg = <0xe2800000 0x1000>;
0191 clock-names = "clk_xin", "clk_ahb";
0192 clocks = <&cru 8>, <&cru 18>;
0193 interrupt-parent = <&gic>;
0194 interrupts = <0 24 4>;
0195 phys = <&emmc_phy>;
0196 phy-names = "phy_arasan";
0197 };
0198
0199 - |
0200 #include <dt-bindings/clock/rk3399-cru.h>
0201 #include <dt-bindings/interrupt-controller/arm-gic.h>
0202 #include <dt-bindings/interrupt-controller/irq.h>
0203 mmc@fe330000 {
0204 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
0205 reg = <0xfe330000 0x10000>;
0206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
0208 clock-names = "clk_xin", "clk_ahb";
0209 arasan,soc-ctl-syscon = <&grf>;
0210 assigned-clocks = <&cru SCLK_EMMC>;
0211 assigned-clock-rates = <200000000>;
0212 clock-output-names = "emmc_cardclock";
0213 phys = <&emmc_phy>;
0214 phy-names = "phy_arasan";
0215 #clock-cells = <0>;
0216 };
0217
0218 - |
0219 mmc@ff160000 {
0220 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
0221 interrupt-parent = <&gic>;
0222 interrupts = <0 48 4>;
0223 reg = <0xff160000 0x1000>;
0224 clocks = <&clk200>, <&clk200>;
0225 clock-names = "clk_xin", "clk_ahb";
0226 clock-output-names = "clk_out_sd0", "clk_in_sd0";
0227 #clock-cells = <1>;
0228 clk-phase-sd-hs = <63>, <72>;
0229 };
0230
0231 - |
0232 mmc@f1040000 {
0233 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
0234 interrupt-parent = <&gic>;
0235 interrupts = <0 126 4>;
0236 reg = <0xf1040000 0x10000>;
0237 clocks = <&clk200>, <&clk200>;
0238 clock-names = "clk_xin", "clk_ahb";
0239 clock-output-names = "clk_out_sd0", "clk_in_sd0";
0240 #clock-cells = <1>;
0241 clk-phase-sd-hs = <132>, <60>;
0242 };
0243
0244 - |
0245 #define LGM_CLK_EMMC5
0246 #define LGM_CLK_NGI
0247 #define LGM_GCLK_EMMC
0248 mmc@ec700000 {
0249 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
0250 reg = <0xec700000 0x300>;
0251 interrupt-parent = <&ioapic1>;
0252 interrupts = <44 1>;
0253 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
0254 <&cgu0 LGM_GCLK_EMMC>;
0255 clock-names = "clk_xin", "clk_ahb", "gate";
0256 clock-output-names = "emmc_cardclock";
0257 #clock-cells = <0>;
0258 phys = <&emmc_phy>;
0259 phy-names = "phy_arasan";
0260 arasan,soc-ctl-syscon = <&sysconf>;
0261 };
0262
0263 - |
0264 #define LGM_CLK_SDIO
0265 #define LGM_GCLK_SDXC
0266 mmc@ec600000 {
0267 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
0268 reg = <0xec600000 0x300>;
0269 interrupt-parent = <&ioapic1>;
0270 interrupts = <43 1>;
0271 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
0272 <&cgu0 LGM_GCLK_SDXC>;
0273 clock-names = "clk_xin", "clk_ahb", "gate";
0274 clock-output-names = "sdxc_cardclock";
0275 #clock-cells = <0>;
0276 phys = <&sdxc_phy>;
0277 phy-names = "phy_arasan";
0278 arasan,soc-ctl-syscon = <&sysconf>;
0279 };
0280
0281 - |
0282 #define KEEM_BAY_PSS_AUX_EMMC
0283 #define KEEM_BAY_PSS_EMMC
0284 mmc@33000000 {
0285 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
0286 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0287 reg = <0x33000000 0x300>;
0288 clock-names = "clk_xin", "clk_ahb";
0289 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
0290 <&scmi_clk KEEM_BAY_PSS_EMMC>;
0291 phys = <&emmc_phy>;
0292 phy-names = "phy_arasan";
0293 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
0294 assigned-clock-rates = <200000000>;
0295 clock-output-names = "emmc_cardclock";
0296 #clock-cells = <0>;
0297 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
0298 };
0299
0300 - |
0301 #define KEEM_BAY_PSS_AUX_SD0
0302 #define KEEM_BAY_PSS_SD0
0303 mmc@31000000 {
0304 compatible = "intel,keembay-sdhci-5.1-sd";
0305 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0306 reg = <0x31000000 0x300>;
0307 clock-names = "clk_xin", "clk_ahb";
0308 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
0309 <&scmi_clk KEEM_BAY_PSS_SD0>;
0310 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
0311 };
0312
0313 - |
0314 #define EMMC_XIN_CLK
0315 #define EMMC_AXI_CLK
0316 #define TBH_PSS_EMMC_RST_N
0317 mmc@80420000 {
0318 compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
0319 interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
0320 reg = <0x80420000 0x400>;
0321 clocks = <&scmi_clk EMMC_XIN_CLK>,
0322 <&scmi_clk EMMC_AXI_CLK>;
0323 clock-names = "clk_xin", "clk_ahb";
0324 phys = <&emmc_phy>;
0325 phy-names = "phy_arasan";
0326 assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
0327 clock-output-names = "emmc_cardclock";
0328 resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
0329 #clock-cells = <0x0>;
0330 };
