0001 Amlogic SD / eMMC controller for S905/GXBB family SoCs
0002
0003 The MMC 5.1 compliant host controller on Amlogic provides the
0004 interface for SD, eMMC and SDIO devices.
0005
0006 This file documents the properties in addition to those available in
0007 the MMC core bindings, documented by mmc.txt.
0008
0009 Required properties:
0010 - compatible : contains one of:
0011 - "amlogic,meson-gx-mmc"
0012 - "amlogic,meson-gxbb-mmc"
0013 - "amlogic,meson-gxl-mmc"
0014 - "amlogic,meson-gxm-mmc"
0015 - "amlogic,meson-axg-mmc"
0016 - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
0017 - clock-names: Should contain the following:
0018 "core" - Main peripheral bus clock
0019 "clkin0" - Parent clock of internal mux
0020 "clkin1" - Other parent clock of internal mux
0021 The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
0022 clock rate requested by the MMC core.
0023 - resets : phandle of the internal reset line
0024
0025 Optional properties:
0026 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
0027 DRAM memory, like on the G12A dedicated SDIO controller.
0028
0029 Example:
0030
0031 sd_emmc_a: mmc@70000 {
0032 compatible = "amlogic,meson-gxbb-mmc";
0033 reg = <0x0 0x70000 0x0 0x2000>;
0034 interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
0035 clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
0036 clock-names = "core", "clkin0", "clkin1";
0037 pinctrl-0 = <&emmc_pins>;
0038 resets = <&reset RESET_SD_EMMC_A>;
0039 };
