0001 * Xilinx SDFEC(16nm) IP *
0002
0003 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
0004 which provides high-throughput LDPC and Turbo Code implementations.
0005 The LDPC decode & encode functionality is capable of covering a range of
0006 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
0007 principally covers codes used by LTE. The FEC Engine offers significant
0008 power and area savings versus implementations done in the FPGA fabric.
0009
0010
0011 Required properties:
0012 - compatible: Must be "xlnx,sd-fec-1.1"
0013 - clock-names : List of input clock names from the following:
0014 - "core_clk", Main processing clock for processing core (required)
0015 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
0016 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
0017 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
0018 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
0019 - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
0020 - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
0021 - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
0022 - clocks : Clock phandles (see clock_bindings.txt for details).
0023 - reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
0024 location and length.
0025 - xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
0026 being used.
0027 - xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
0028 driven with a fixed value and is not present on the device, a value of 1
0029 configures the DIN_WORDS to be block based, while a value of 2 configures the
0030 DIN_WORDS input to be supplied for each AXI transaction.
0031 - xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
0032 configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
0033 of "4x128b".
0034 - xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
0035 driven with a fixed value and is not present on the device, a value of 1
0036 configures the DOUT_WORDS to be block based, while a value of 2 configures the
0037 DOUT_WORDS input to be supplied for each AXI transaction.
0038 - xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
0039 configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
0040 of "4x128b".
0041 Optional properties:
0042 - interrupts: should contain SDFEC interrupt number
0043
0044 Example
0045 ---------------------------------------
0046 sd_fec_0: sd-fec@a0040000 {
0047 compatible = "xlnx,sd-fec-1.1";
0048 clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
0049 clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
0050 reg = <0x0 0xa0040000 0x0 0x40000>;
0051 interrupt-parent = <&axi_intc>;
0052 interrupts = <1 0>;
0053 xlnx,sdfec-code = "ldpc";
0054 xlnx,sdfec-din-words = <0>;
0055 xlnx,sdfec-din-width = <2>;
0056 xlnx,sdfec-dout-words = <0>;
0057 xlnx,sdfec-dout-width = <1>;
0058 };
