0001 * Microsemi MIPS CPUs
0002
0003 Boards with a SoC of the Microsemi MIPS family shall have the following
0004 properties:
0005
0006 Required properties:
0007 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
0008
0009
0010 * Other peripherals:
0011
0012 o CPU chip regs:
0013
0014 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
0015 functionalities: chip ID, general purpose register for software use, reset
0016 controller, hardware status and configuration, efuses.
0017
0018 Required properties:
0019 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
0020 - reg : Should contain registers location and length
0021
0022 Example:
0023 syscon@71070000 {
0024 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
0025 reg = <0x71070000 0x1c>;
0026 };
0027
0028
0029 o CPU system control:
0030
0031 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
0032 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
0033 endianness, CPU bus control, CPU status.
0034
0035 Required properties:
0036 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
0037 - reg : Should contain registers location and length
0038
0039 Example:
0040 syscon@70000000 {
0041 compatible = "mscc,ocelot-cpu-syscon", "syscon";
0042 reg = <0x70000000 0x2c>;
0043 };
0044
0045 o HSIO regs:
0046
0047 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
0048 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
0049 status, SerDes muxing and a thermal sensor.
0050
0051 Required properties:
0052 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
0053 - reg : Should contain registers location and length
0054
0055 Example:
0056 syscon@10d0000 {
0057 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
0058 reg = <0x10d0000 0x10000>;
0059 };
