0001 Imagination University Program MIPSfpga
0002 =======================================
0003
0004 Under the Imagination University Program, a microAptiv UP core has been
0005 released for academic usage.
0006
0007 As we are dealing with a MIPS core instantiated on an FPGA, specifications
0008 are fluid and can be varied in RTL.
0009
0010 This binding document is provided as baseline guidance for the example
0011 project provided by IMG.
0012
0013 The example project runs on the Nexys4DDR board by Digilent powered by
0014 the ARTIX-7 FPGA by Xilinx.
0015
0016 Relevant details about the example project and the Nexys4DDR board:
0017
0018 - microAptiv UP core m14Kc
0019 - 50MHz clock speed
0020 - 128Mbyte DDR RAM at 0x0000_0000
0021 - 8Kbyte RAM at 0x1000_0000
0022 - axi_intc at 0x1020_0000
0023 - axi_uart16550 at 0x1040_0000
0024 - axi_gpio at 0x1060_0000
0025 - axi_i2c at 0x10A0_0000
0026 - custom_gpio at 0x10C0_0000
0027 - axi_ethernetlite at 0x10E0_0000
0028 - 8Kbyte BootRAM at 0x1FC0_0000
0029
0030 Required properties:
0031 --------------------
0032 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".
0033
0034 CPU nodes:
0035 ----------
0036 A "cpus" node is required. Required properties:
0037 - #address-cells: Must be 1.
0038 - #size-cells: Must be 0.
0039 A CPU sub-node is also required for at least CPU 0. Required properties:
0040 - device_type: Must be "cpu".
0041 - compatible: Must be "mips,m14Kc".
0042 - reg: Must be <0>.
0043 - clocks: phandle to ext clock for fixed-clock received by MIPS core.
0044
0045 Example:
0046
0047 compatible = "img,xilfpga","digilent,nexys4ddr";
0048 cpus {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 cpu0: cpu@0 {
0053 device_type = "cpu";
0054 compatible = "mips,m14Kc";
0055 reg = <0>;
0056 clocks = <&ext>;
0057 };
0058 };
0059
0060 ext: ext {
0061 compatible = "fixed-clock";
0062 #clock-cells = <0>;
0063 clock-frequency = <50000000>;
0064 };
0065
0066 Boot protocol:
0067 --------------
0068
0069 The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
0070 This is for easy reprogrammibility via JTAG.
0071
0072 The BootRAM initializes the cache and the axi_uart peripheral.
0073
0074 DDR initialization is already handled by a HW IP block.
0075
0076 When the example project bitstream is loaded, the cpu_reset button
0077 needs to be pressed.
0078
0079 The bootram initializes the cache and axi_uart.
0080 Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.
0081
0082 At this point, the board is ready to load the Linux kernel
0083 vmlinux file via JTAG.
