bindings/mips/cpu_irq.txt

0001 MIPS CPU interrupt controller
0002
0003 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
0004 IRQs from a devicetree file and create a irq_domain for IRQ controller.
0005
0006 With the irq_domain in place we can describe how the 8 IRQs are wired to the
0007 platforms internal interrupt controller cascade.
0008
0009 Below is an example of a platform describing the cascade inside the devicetree
0010 and the code used to load it inside arch_init_irq().
0011
0012 Required properties:
0013 - compatible : Should be "mti,cpu-interrupt-controller"
0014
0015 Example devicetree:
0016         cpu-irq: cpu-irq {
0017                 #address-cells = <0>;
0018
0019                 interrupt-controller;
0020                 #interrupt-cells = <1>;
0021
0022                 compatible = "mti,cpu-interrupt-controller";
0023         };
0024
0025         intc: intc@200 {
0026                 compatible = "ralink,rt2880-intc";
0027                 reg = <0x200 0x100>;
0028
0029                 interrupt-controller;
0030                 #interrupt-cells = <1>;
0031
0032                 interrupt-parent = <&cpu-irq>;
0033                 interrupts = <2>;
0034         };
0035
0036
0037 Example platform irq.c:
0038 static struct of_device_id __initdata of_irq_ids[] = {
0039         { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
0040         { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
0041         {},
0042 };
0043
0044 void __init arch_init_irq(void)
0045 {
0046         of_irq_init(of_irq_ids);
0047 }