0001 * UCTL SATA controller glue
0002
0003 UCTL is the bridge unit between the I/O interconnect (an internal bus)
0004 and the SATA AHCI host controller (UAHC). It performs the following functions:
0005 - provides interfaces for the applications to access the UAHC AHCI
0006 registers on the CN71XX I/O space.
0007 - provides a bridge for UAHC to fetch AHCI command table entries and data
0008 buffers from Level 2 Cache.
0009 - posts interrupts to the CIU.
0010 - contains registers that:
0011 - control the behavior of the UAHC
0012 - control the clock/reset generation to UAHC
0013 - control endian swapping for all UAHC registers and DMA accesses
0014
0015 Properties:
0016
0017 - compatible: "cavium,octeon-7130-sata-uctl"
0018
0019 Compatibility with the cn7130 SOC.
0020
0021 - reg: The base address of the UCTL register bank.
0022
0023 - #address-cells, #size-cells, ranges and dma-ranges must be present and hold
0024 suitable values to map all child nodes.
0025
0026 Example:
0027
0028 uctl@118006c000000 {
0029 compatible = "cavium,octeon-7130-sata-uctl";
0030 reg = <0x11800 0x6c000000 0x0 0x100>;
0031 ranges; /* Direct mapping */
0032 dma-ranges;
0033 #address-cells = <2>;
0034 #size-cells = <2>;
0035
0036 sata: sata@16c0000000000 {
0037 compatible = "cavium,octeon-7130-ahci";
0038 reg = <0x16c00 0x00000000 0x0 0x200>;
0039 interrupt-parent = <&cibsata>;
0040 interrupts = <2 4>; /* Bit: 2, level */
0041 };
0042 };
