mips/cavium/ciu.txt

0001 * Central Interrupt Unit
0002
0003 Properties:
0004 - compatible: "cavium,octeon-3860-ciu"
0005
0006   Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
0007
0008 - interrupt-controller:  This is an interrupt controller.
0009
0010 - reg: The base address of the CIU's register bank.
0011
0012 - #interrupt-cells: Must be <2>.  The first cell is the bank within
0013    the CIU and may have a value of 0 or 1.  The second cell is the bit
0014    within the bank and may have a value between 0 and 63.
0015
0016 Example:
0017         interrupt-controller@1070000000000 {
0018                 compatible = "cavium,octeon-3860-ciu";
0019                 interrupt-controller;
0020                 /* Interrupts are specified by two parts:
0021                  * 1) Controller register (0 or 1)
0022                  * 2) Bit within the register (0..63)
0023                  */
0024                 #interrupt-cells = <2>;
0025                 reg = <0x10700 0x00000000 0x0 0x7000>;
0026         };