Back to home page

OSCL-LXR

 
 

    


0001 * Cavium Interrupt Bus widget
0002 
0003 Properties:
0004 - compatible: "cavium,octeon-7130-cib"
0005 
0006   Compatibility with cn70XX SoCs.
0007 
0008 - interrupt-controller:  This is an interrupt controller.
0009 
0010 - reg: Two elements consisting of the addresses of the RAW and EN
0011   registers of the CIB block
0012 
0013 - cavium,max-bits: The index (zero based) of the highest numbered bit
0014   in the CIB block.
0015 
0016 - interrupts: The CIU line to which the CIB block is connected.
0017 
0018 - #interrupt-cells: Must be <2>.  The first cell is the bit within the
0019    CIB.  The second cell specifies the triggering semantics of the
0020    line.
0021 
0022 Example:
0023 
0024         interrupt-controller@107000000e000 {
0025                 compatible = "cavium,octeon-7130-cib";
0026                 reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
0027                       <0x10700 0x0000e100 0x0 0x8>; /* EN */
0028                 cavium,max-bits = <23>;
0029 
0030                 interrupt-controller;
0031                 interrupt-parent = <&ciu>;
0032                 interrupts = <1 24>;
0033                 /* Interrupts are specified by two parts:
0034                  * 1) Bit number in the CIB* registers
0035                  * 2) Triggering (1 - edge rising
0036                  *                2 - edge falling
0037                  *                4 - level active high
0038                  *                8 - level active low)
0039                  */
0040                 #interrupt-cells = <2>;
0041         };