0001 * Boot Bus
0002
0003 The Octeon Boot Bus is a configurable parallel bus with 8 chip
0004 selects. Each chip select is independently configurable.
0005
0006 Properties:
0007 - compatible: "cavium,octeon-3860-bootbus"
0008
0009 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
0010
0011 - reg: The base address of the Boot Bus' register bank.
0012
0013 - #address-cells: Must be <2>. The first cell is the chip select
0014 within the bootbus. The second cell is the offset from the chip select.
0015
0016 - #size-cells: Must be <1>.
0017
0018 - ranges: There must be one one triplet of (child-bus-address,
0019 parent-bus-address, length) for each active chip select. If the
0020 length element for any triplet is zero, the chip select is disabled,
0021 making it inactive.
0022
0023 The configuration parameters for each chip select are stored in child
0024 nodes.
0025
0026 Configuration Properties:
0027 - compatible: "cavium,octeon-3860-bootbus-config"
0028
0029 - cavium,cs-index: A single cell indicating the chip select that
0030 corresponds to this configuration.
0031
0032 - cavium,t-adr: A cell specifying the ADR timing (in nS).
0033
0034 - cavium,t-ce: A cell specifying the CE timing (in nS).
0035
0036 - cavium,t-oe: A cell specifying the OE timing (in nS).
0037
0038 - cavium,t-we: A cell specifying the WE timing (in nS).
0039
0040 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
0041
0042 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
0043
0044 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
0045
0046 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
0047
0048 - cavium,t-page: A cell specifying the PAGE timing (in nS).
0049
0050 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
0051
0052 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
0053 = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
0054
0055 - cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected.
0056
0057 - cavium,page-mode: Optional. If present, page mode (PAGEM) is selected.
0058
0059 - cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
0060 the bus for this chip select.
0061
0062 - cavium,ale-mode: Optional. If present, ALE mode is selected.
0063
0064 - cavium,sam-mode: Optional. If present, SAM mode is selected.
0065
0066 - cavium,or-mode: Optional. If present, OR mode is selected.
0067
0068 Example:
0069 bootbus: bootbus@1180000000000 {
0070 compatible = "cavium,octeon-3860-bootbus";
0071 reg = <0x11800 0x00000000 0x0 0x200>;
0072 /* The chip select number and offset */
0073 #address-cells = <2>;
0074 /* The size of the chip select region */
0075 #size-cells = <1>;
0076 ranges = <0 0 0x0 0x1f400000 0xc00000>,
0077 <1 0 0x10000 0x30000000 0>,
0078 <2 0 0x10000 0x40000000 0>,
0079 <3 0 0x10000 0x50000000 0>,
0080 <4 0 0x0 0x1d020000 0x10000>,
0081 <5 0 0x0 0x1d040000 0x10000>,
0082 <6 0 0x0 0x1d050000 0x10000>,
0083 <7 0 0x10000 0x90000000 0>;
0084
0085 cavium,cs-config@0 {
0086 compatible = "cavium,octeon-3860-bootbus-config";
0087 cavium,cs-index = <0>;
0088 cavium,t-adr = <20>;
0089 cavium,t-ce = <60>;
0090 cavium,t-oe = <60>;
0091 cavium,t-we = <45>;
0092 cavium,t-rd-hld = <35>;
0093 cavium,t-wr-hld = <45>;
0094 cavium,t-pause = <0>;
0095 cavium,t-wait = <0>;
0096 cavium,t-page = <35>;
0097 cavium,t-rd-dly = <0>;
0098
0099 cavium,pages = <0>;
0100 cavium,bus-width = <8>;
0101 };
0102 .
0103 .
0104 .
0105 cavium,cs-config@6 {
0106 compatible = "cavium,octeon-3860-bootbus-config";
0107 cavium,cs-index = <6>;
0108 cavium,t-adr = <5>;
0109 cavium,t-ce = <300>;
0110 cavium,t-oe = <270>;
0111 cavium,t-we = <150>;
0112 cavium,t-rd-hld = <100>;
0113 cavium,t-wr-hld = <70>;
0114 cavium,t-pause = <0>;
0115 cavium,t-wait = <0>;
0116 cavium,t-page = <320>;
0117 cavium,t-rd-dly = <0>;
0118
0119 cavium,pages = <0>;
0120 cavium,wait-mode;
0121 cavium,bus-width = <16>;
0122 };
0123 .
0124 .
0125 .
0126 };
