mips/brcm/soc.txt

0001 * Broadcom cable/DSL/settop platforms
0002
0003 Required properties:
0004
0005 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
0006               "brcm,bcm3384-viper", "brcm,bcm33843-viper"
0007               "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
0008               "brcm,bcm63168", "brcm,bcm63268",
0009               "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
0010               "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
0011
0012 The experimental -viper variants are for running Linux on the 3384's
0013 BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
0014
0015 Power management
0016 ----------------
0017
0018 For power management (particularly, S2/S3/S5 system suspend), the following SoC
0019 components are needed:
0020
0021 = Always-On control block (AON CTRL)
0022
0023 This hardware provides control registers for the "always-on" (even in low-power
0024 modes) hardware, such as the Power Management State Machine (PMSM).
0025
0026 Required properties:
0027 - compatible     : should be one of
0028                    "brcm,bcm7425-aon-ctrl"
0029                    "brcm,bcm7429-aon-ctrl"
0030                    "brcm,bcm7435-aon-ctrl" and
0031                    "brcm,brcmstb-aon-ctrl"
0032 - reg            : the register start and length for the AON CTRL block
0033
0034 Example:
0035
0036 syscon@410000 {
0037         compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
0038         reg = <0x410000 0x400>;
0039 };
0040
0041 = Memory controllers
0042
0043 A Broadcom STB SoC typically has a number of independent memory controllers,
0044 each of which may have several associated hardware blocks, which are versioned
0045 independently (control registers, DDR PHYs, etc.). One might consider
0046 describing these controllers as a parent "memory controllers" block, which
0047 contains N sub-nodes (one for each controller in the system), each of which is
0048 associated with a number of hardware register resources (e.g., its PHY.
0049
0050 == MEMC (MEMory Controller)
0051
0052 Represents a single memory controller instance.
0053
0054 Required properties:
0055 - compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
0056 - ranges         : should contain the child address in the parent address
0057                    space, must be 0 here, and the register start and length of
0058                    the entire memory controller (including all sub nodes: DDR PHY,
0059                    arbiter, etc.)
0060 - #address-cells : must be 1
0061 - #size-cells    : must be 1
0062
0063 Example:
0064
0065         memory-controller@0 {
0066                 compatible = "brcm,brcmstb-memc", "simple-bus";
0067                 ranges = <0x0 0x0 0xa000>;
0068                 #address-cells = <1>;
0069                 #size-cells = <1>;
0070
0071                 memc-arb@1000 {
0072                         ...
0073                 };
0074
0075                 memc-ddr@2000 {
0076                         ...
0077                 };
0078
0079                 ddr-phy@6000 {
0080                         ...
0081                 };
0082         };
0083
0084 Should contain subnodes for any of the following relevant hardware resources:
0085
0086 == DDR PHY control
0087
0088 Control registers for this memory controller's DDR PHY.
0089
0090 Required properties:
0091 - compatible     : should contain one of these
0092                    "brcm,brcmstb-ddr-phy-v64.5"
0093                    "brcm,brcmstb-ddr-phy"
0094
0095 - reg            : the DDR PHY register range and length
0096
0097 Example:
0098
0099         ddr-phy@6000 {
0100                 compatible = "brcm,brcmstb-ddr-phy-v64.5";
0101                 reg = <0x6000 0xc8>;
0102         };
0103
0104 == DDR memory controller sequencer
0105
0106 Control registers for this memory controller's DDR memory sequencer
0107
0108 Required properties:
0109 - compatible     : should contain one of these
0110                    "brcm,bcm7425-memc-ddr"
0111                    "brcm,bcm7429-memc-ddr"
0112                    "brcm,bcm7435-memc-ddr" and
0113                    "brcm,brcmstb-memc-ddr"
0114
0115 - reg            : the DDR sequencer register range and length
0116
0117 Example:
0118
0119         memc-ddr@2000 {
0120                 compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
0121                 reg = <0x2000 0x300>;
0122         };
0123
0124 == MEMC Arbiter
0125
0126 The memory controller arbiter is responsible for memory clients allocation
0127 (bandwidth, priorities etc.) and needs to have its contents restored during
0128 deep sleep states (S3).
0129
0130 Required properties:
0131
0132 - compatible    : should contain one of these
0133                   "brcm,brcmstb-memc-arb-v10.0.0.0"
0134                   "brcm,brcmstb-memc-arb"
0135
0136 - reg           : the DDR Arbiter register range and length
0137
0138 Example:
0139
0140         memc-arb@1000 {
0141                 compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
0142                 reg = <0x1000 0x248>;
0143         };
0144
0145 == Timers
0146
0147 The Broadcom STB chips contain a timer block with several general purpose
0148 timers that can be used.
0149
0150 Required properties:
0151
0152 - compatible    : should contain one of:
0153                   "brcm,bcm7425-timers"
0154                   "brcm,bcm7429-timers"
0155                   "brcm,bcm7435-timers" and
0156                   "brcm,brcmstb-timers"
0157 - reg           : the timers register range
0158 - interrupts    : the interrupt line for this timer block
0159
0160 Example:
0161
0162         timers: timer@4067c0 {
0163                 compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
0164                 reg = <0x4067c0 0x40>;
0165                 interrupts = <&periph_intc 19>;
0166         };