0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: TI J721e System Controller Registers R/W Device Tree Bindings
0009
0010 description: |
0011 This represents the Control Module registers (CTRL_MMR0) on the SoC.
0012 System controller node represents a register region containing a set
0013 of miscellaneous registers. The registers are not cohesive enough to
0014 represent as any specific type of device. The typical use-case is
0015 for some other node's driver, or platform-specific code, to acquire
0016 a reference to the syscon node (e.g. by phandle, node path, or
0017 search using a specific compatible value), interrogate the node (or
0018 associated OS driver) to determine the location of the registers,
0019 and access the registers directly.
0020
0021 maintainers:
0022 - Kishon Vijay Abraham I <kishon@ti.com>
0023 - Roger Quadros <rogerq@kernel.org>
0024
0025 properties:
0026 compatible:
0027 items:
0028 - enum:
0029 - ti,j721e-system-controller
0030 - const: syscon
0031 - const: simple-mfd
0032
0033 reg:
0034 maxItems: 1
0035
0036 "#address-cells":
0037 const: 1
0038
0039 "#size-cells":
0040 const: 1
0041
0042 ranges: true
0043
0044 patternProperties:
0045 # Optional children
0046 "^mux-controller@[0-9a-f]+$":
0047 type: object
0048 description:
0049 This is the SERDES lane control mux.
0050
0051 "^clock-controller@[0-9a-f]+$":
0052 type: object
0053 $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
0054 description:
0055 Clock provider for TI EHRPWM nodes.
0056
0057 required:
0058 - compatible
0059 - reg
0060 - "#address-cells"
0061 - "#size-cells"
0062 - ranges
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068 scm_conf: scm-conf@100000 {
0069 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
0070 reg = <0x00100000 0x1c000>;
0071 #address-cells = <1>;
0072 #size-cells = <1>;
0073 ranges;
0074
0075 serdes_ln_ctrl: mux-controller@4080 {
0076 compatible = "mmio-mux";
0077 reg = <0x00004080 0x50>;
0078
0079 #mux-control-cells = <1>;
0080 mux-reg-masks =
0081 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
0082 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
0083 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
0084 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
0085 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
0086 /* SERDES4 lane0/1/2/3 select */
0087 };
0088
0089 clock-controller@4140 {
0090 compatible = "ti,am654-ehrpwm-tbclk", "syscon";
0091 reg = <0x4140 0x18>;
0092 #clock-cells = <1>;
0093 };
0094 };
0095 ...
