0001 OMAP HS USB Host
0002
0003 Required properties:
0004
0005 - compatible: should be "ti,usbhs-host"
0006 - reg: should contain one register range i.e. start and length
0007 - ti,hwmods: must contain "usb_host_hs"
0008
0009 Optional properties:
0010
0011 - num-ports: number of USB ports. Usually this is automatically detected
0012 from the IP's revision register but can be overridden by specifying
0013 this property. A maximum of 3 ports are supported at the moment.
0014
0015 - portN-mode: String specifying the port mode for port N, where N can be
0016 from 1 to 3. If the port mode is not specified, that port is treated
0017 as unused. When specified, it must be one of the following.
0018 "ehci-phy",
0019 "ehci-tll",
0020 "ehci-hsic",
0021 "ohci-phy-6pin-datse0",
0022 "ohci-phy-6pin-dpdm",
0023 "ohci-phy-3pin-datse0",
0024 "ohci-phy-4pin-dpdm",
0025 "ohci-tll-6pin-datse0",
0026 "ohci-tll-6pin-dpdm",
0027 "ohci-tll-3pin-datse0",
0028 "ohci-tll-4pin-dpdm",
0029 "ohci-tll-2pin-datse0",
0030 "ohci-tll-2pin-dpdm",
0031
0032 - single-ulpi-bypass: Must be present if the controller contains a single
0033 ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
0034
0035 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
0036 clock-names.
0037
0038 - clock-names: should include:
0039 For OMAP3
0040 * "usbhost_120m_fck" - 120MHz Functional clock.
0041
0042 For OMAP4+
0043 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
0044 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
0045 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
0046 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
0047 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
0048 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
0049 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
0050 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
0051 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
0052 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
0053 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
0054 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
0055 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
0056 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
0057
0058 Required properties if child node exists:
0059
0060 - #address-cells: Must be 1
0061 - #size-cells: Must be 1
0062 - ranges: must be present
0063
0064 Properties for children:
0065
0066 The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
0067 See Documentation/devicetree/bindings/usb/ehci-omap.txt and
0068 Documentation/devicetree/bindings/usb/ohci-omap3.txt.
0069
0070 Example for OMAP4:
0071
0072 usbhshost: usbhshost@4a064000 {
0073 compatible = "ti,usbhs-host";
0074 reg = <0x4a064000 0x800>;
0075 ti,hwmods = "usb_host_hs";
0076 #address-cells = <1>;
0077 #size-cells = <1>;
0078 ranges;
0079
0080 usbhsohci: ohci@4a064800 {
0081 compatible = "ti,ohci-omap3", "usb-ohci";
0082 reg = <0x4a064800 0x400>;
0083 interrupt-parent = <&gic>;
0084 interrupts = <0 76 0x4>;
0085 };
0086
0087 usbhsehci: ehci@4a064c00 {
0088 compatible = "ti,ehci-omap", "usb-ehci";
0089 reg = <0x4a064c00 0x400>;
0090 interrupt-parent = <&gic>;
0091 interrupts = <0 77 0x4>;
0092 };
0093 };
0094
0095 &usbhshost {
0096 port1-mode = "ehci-phy";
0097 port2-mode = "ehci-tll";
0098 port3-mode = "ehci-phy";
0099 };
0100
0101 &usbhsehci {
0102 phys = <&hsusb1_phy 0 &hsusb3_phy>;
0103 };
