0001 MAX77620 Power management IC from Maxim Semiconductor.
0002
0003 Required properties:
0004 -------------------
0005 - compatible: Must be one of
0006 "maxim,max77620"
0007 "maxim,max20024"
0008 "maxim,max77663"
0009 - reg: I2C device address.
0010
0011 Optional properties:
0012 -------------------
0013 - interrupts: The interrupt on the parent the controller is
0014 connected to.
0015 - interrupt-controller: Marks the device node as an interrupt controller.
0016 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
0017 variant of <../interrupt-controller/interrupts.txt>
0018 IRQ numbers for different interrupt source of MAX77620
0019 are defined at dt-bindings/mfd/max77620.h.
0020
0021 - system-power-controller: Indicates that this PMIC is controlling the
0022 system power, see [1] for more details.
0023
0024 [1] Documentation/devicetree/bindings/power/power-controller.txt
0025
0026 Optional subnodes and their properties:
0027 =======================================
0028
0029 Flexible power sequence configurations:
0030 --------------------------------------
0031 The Flexible Power Sequencer (FPS) allows each regulator to power up under
0032 hardware or software control. Additionally, each regulator can power on
0033 independently or among a group of other regulators with an adjustable power-up
0034 and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
0035 to be part of a sequence allowing external regulators to be sequenced along
0036 with internal regulators. 32KHz clock can be programmed to be part of a
0037 sequence.
0038
0039 The flexible sequencing structure consists of two hardware enable inputs
0040 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
0041 Each master sequencing timer is programmable through its configuration
0042 register to have a hardware enable source (EN1 or EN2) or a software enable
0043 source (SW). When enabled/disabled, the master sequencing timer generates
0044 eight sequencing events on different time periods called slots. The time
0045 period between each event is programmable within the configuration register.
0046 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
0047 sequence slave register which allows its enable source to be specified as
0048 a flexible power sequencer timer or a software bit. When a FPS source of
0049 regulators, GPIOs and clocks specifies the enable source to be a flexible
0050 power sequencer, the power up and power down delays can be specified in
0051 the regulators, GPIOs and clocks flexible power sequencer configuration
0052 registers.
0053
0054 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
0055 clock are set into following state at the sequencing event that
0056 corresponds to its flexible sequencer configuration register.
0057 Sleep state: In this state, regulators, GPIOs
0058 and 32KHz clock get disabled at
0059 the sequencing event.
0060 Global Low Power Mode (GLPM): In this state, regulators are set in
0061 low power mode at the sequencing event.
0062
0063 The configuration parameters of FPS is provided through sub-node "fps"
0064 and their child for FPS specific. The child node name for FPS are "fps0",
0065 "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
0066
0067 The FPS configurations like FPS source, power up and power down slots for
0068 regulators, GPIOs and 32kHz clocks are provided in their respective
0069 configuration nodes which is explained in respective sub-system DT
0070 binding document.
0071
0072 There is need for different FPS configuration parameters based on system
0073 state like when system state changed from active to suspend or active to
0074 power off (shutdown).
0075
0076 Optional properties:
0077 -------------------
0078 -maxim,fps-event-source: u32, FPS event source like external
0079 hardware input to PMIC i.e. EN0, EN1 or
0080 software (SW).
0081 The macros are defined on
0082 dt-bindings/mfd/max77620.h
0083 for different control source.
0084 - MAX77620_FPS_EVENT_SRC_EN0
0085 for hardware input pin EN0.
0086 - MAX77620_FPS_EVENT_SRC_EN1
0087 for hardware input pin EN1.
0088 - MAX77620_FPS_EVENT_SRC_SW
0089 for software control.
0090
0091 -maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
0092 when system enters in to shutdown
0093 state.
0094
0095 -maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
0096 when system enters in to suspend state.
0097
0098 -maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
0099 event cleared (set to LOW) whether it
0100 should go to sleep state or low-power
0101 state. Following are valid values:
0102 - MAX77620_FPS_INACTIVE_STATE_SLEEP
0103 to set the PMIC state to sleep.
0104 - MAX77620_FPS_INACTIVE_STATE_LOW_POWER
0105 to set the PMIC state to low
0106 power.
0107 Absence of this property or other value
0108 will not change device state when FPS
0109 event get cleared.
0110
0111 Here supported time periods by device in microseconds are as follows:
0112 MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
0113 MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
0114 MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
0115
0116 -maxim,power-ok-control: configure map power ok bit
0117 1: Enables POK(Power OK) to control nRST_IO and GPIO1
0118 POK function.
0119 0: Disables POK control.
0120 if property missing, do not configure MPOK bit.
0121 If POK mapping is enabled for GPIO1/nRST_IO then,
0122 GPIO1/nRST_IO pins are HIGH only if all rails
0123 that have POK control enabled are HIGH.
0124 If any of the rails goes down(which are enabled for POK
0125 control) then, GPIO1/nRST_IO goes LOW.
0126 this property is valid for max20024 only.
0127
0128 For DT binding details of different sub modules like GPIO, pincontrol,
0129 regulator, power, please refer respective device-tree binding document
0130 under their respective sub-system directories.
0131
0132 Example:
0133 --------
0134 #include <dt-bindings/mfd/max77620.h>
0135
0136 max77620@3c {
0137 compatible = "maxim,max77620";
0138 reg = <0x3c>;
0139
0140 interrupt-parent = <&intc>;
0141 interrupts = <0 86 IRQ_TYPE_NONE>;
0142
0143 interrupt-controller;
0144 #interrupt-cells = <2>;
0145
0146 fps {
0147 fps0 {
0148 maxim,shutdown-fps-time-period-us = <1280>;
0149 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
0150 };
0151
0152 fps1 {
0153 maxim,shutdown-fps-time-period-us = <1280>;
0154 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
0155 };
0156
0157 fps2 {
0158 maxim,shutdown-fps-time-period-us = <1280>;
0159 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
0160 };
0161 };
0162 };
