0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
0008
0009 maintainers:
0010 - Liu Ying <victor.liu@nxp.com>
0011
0012 description: |
0013 As a system controller, the Freescale i.MX8qm/qxp Control and Status
0014 Registers(CSR) module represents a set of miscellaneous registers of a
0015 specific subsystem. It may provide control and/or status report interfaces
0016 to a mix of standalone hardware devices within that subsystem. One typical
0017 use-case is for some other nodes to acquire a reference to the syscon node
0018 by phandle, and the other typical use-case is that the operating system
0019 should consider all subnodes of the CSR module as separate child devices.
0020
0021 properties:
0022 $nodename:
0023 pattern: "^syscon@[0-9a-f]+$"
0024
0025 compatible:
0026 items:
0027 - enum:
0028 - fsl,imx8qxp-mipi-lvds-csr
0029 - fsl,imx8qm-lvds-csr
0030 - const: syscon
0031 - const: simple-mfd
0032
0033 reg:
0034 maxItems: 1
0035
0036 clocks:
0037 maxItems: 1
0038
0039 clock-names:
0040 const: ipg
0041
0042 patternProperties:
0043 "^(ldb|phy|pxl2dpi)$":
0044 type: object
0045 description: The possible child devices of the CSR module.
0046
0047 required:
0048 - compatible
0049 - reg
0050 - clocks
0051 - clock-names
0052
0053 allOf:
0054 - if:
0055 properties:
0056 compatible:
0057 contains:
0058 const: fsl,imx8qxp-mipi-lvds-csr
0059 then:
0060 required:
0061 - pxl2dpi
0062 - ldb
0063
0064 - if:
0065 properties:
0066 compatible:
0067 contains:
0068 const: fsl,imx8qm-lvds-csr
0069 then:
0070 required:
0071 - phy
0072 - ldb
0073
0074 additionalProperties: false
0075
0076 examples:
0077 - |
0078 #include <dt-bindings/clock/imx8-lpcg.h>
0079 #include <dt-bindings/firmware/imx/rsrc.h>
0080 mipi_lvds_0_csr: syscon@56221000 {
0081 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
0082 reg = <0x56221000 0x1000>;
0083 clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
0084 clock-names = "ipg";
0085
0086 mipi_lvds_0_pxl2dpi: pxl2dpi {
0087 compatible = "fsl,imx8qxp-pxl2dpi";
0088 fsl,sc-resource = <IMX_SC_R_MIPI_0>;
0089 power-domains = <&pd IMX_SC_R_MIPI_0>;
0090
0091 ports {
0092 #address-cells = <1>;
0093 #size-cells = <0>;
0094
0095 port@0 {
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098 reg = <0>;
0099
0100 mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
0101 reg = <0>;
0102 remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
0103 };
0104
0105 mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
0106 reg = <1>;
0107 remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
0108 };
0109 };
0110
0111 port@1 {
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 reg = <1>;
0115
0116 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
0117 reg = <0>;
0118 remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
0119 };
0120
0121 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
0122 reg = <1>;
0123 remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
0124 };
0125 };
0126 };
0127 };
0128
0129 mipi_lvds_0_ldb: ldb {
0130 #address-cells = <1>;
0131 #size-cells = <0>;
0132 compatible = "fsl,imx8qxp-ldb";
0133 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
0134 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
0135 clock-names = "pixel", "bypass";
0136 power-domains = <&pd IMX_SC_R_LVDS_0>;
0137
0138 channel@0 {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 reg = <0>;
0142 phys = <&mipi_lvds_0_phy>;
0143 phy-names = "lvds_phy";
0144
0145 port@0 {
0146 reg = <0>;
0147
0148 mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
0149 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
0150 };
0151 };
0152
0153 port@1 {
0154 reg = <1>;
0155
0156 /* ... */
0157 };
0158 };
0159
0160 channel@1 {
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 reg = <1>;
0164 phys = <&mipi_lvds_0_phy>;
0165 phy-names = "lvds_phy";
0166
0167 port@0 {
0168 reg = <0>;
0169
0170 mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
0171 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
0172 };
0173 };
0174
0175 port@1 {
0176 reg = <1>;
0177
0178 /* ... */
0179 };
0180 };
0181 };
0182 };
0183
0184 mipi_lvds_0_phy: phy@56228300 {
0185 compatible = "fsl,imx8qxp-mipi-dphy";
0186 reg = <0x56228300 0x100>;
0187 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
0188 clock-names = "phy_ref";
0189 #phy-cells = <0>;
0190 fsl,syscon = <&mipi_lvds_0_csr>;
0191 power-domains = <&pd IMX_SC_R_MIPI_0>;
0192 };
