0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Álvaro Fernández Rojas <noltari@gmail.com>
0011 - Jonas Gorski <jonas.gorski@gmail.com>
0012
0013 description:
0014 Broadcom BCM63268 SoC GPIO system controller which provides a register map
0015 for controlling the GPIO and pins of the SoC.
0016
0017 properties:
0018 "#address-cells": true
0019
0020 "#size-cells": true
0021
0022 compatible:
0023 items:
0024 - const: brcm,bcm63268-gpio-sysctl
0025 - const: syscon
0026 - const: simple-mfd
0027
0028 ranges:
0029 maxItems: 1
0030
0031 reg:
0032 maxItems: 1
0033
0034 patternProperties:
0035 "^gpio@[0-9a-f]+$":
0036 # Child node
0037 type: object
0038 $ref: "../gpio/brcm,bcm6345-gpio.yaml"
0039 description:
0040 GPIO controller for the SoC GPIOs. This child node definition
0041 should follow the bindings specified in
0042 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
0043
0044 "^pinctrl@[0-9a-f]+$":
0045 # Child node
0046 type: object
0047 $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
0048 description:
0049 Pin controller for the SoC pins. This child node definition
0050 should follow the bindings specified in
0051 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
0052
0053 required:
0054 - "#address-cells"
0055 - compatible
0056 - ranges
0057 - reg
0058 - "#size-cells"
0059
0060 additionalProperties: false
0061
0062 examples:
0063 - |
0064 syscon@100000c0 {
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
0068 reg = <0x100000c0 0x80>;
0069 ranges = <0 0x100000c0 0x80>;
0070
0071 gpio@0 {
0072 compatible = "brcm,bcm63268-gpio";
0073 reg-names = "dirout", "dat";
0074 reg = <0x0 0x8>, <0x8 0x8>;
0075
0076 gpio-controller;
0077 gpio-ranges = <&pinctrl 0 0 52>;
0078 #gpio-cells = <2>;
0079 };
0080
0081 pinctrl: pinctrl@10 {
0082 compatible = "brcm,bcm63268-pinctrl";
0083 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
0084
0085 pinctrl_serial_led: serial_led-pins {
0086 pinctrl_serial_led_clk: serial_led_clk-pins {
0087 function = "serial_led_clk";
0088 pins = "gpio0";
0089 };
0090
0091 pinctrl_serial_led_data: serial_led_data-pins {
0092 function = "serial_led_data";
0093 pins = "gpio1";
0094 };
0095 };
0096
0097 pinctrl_hsspi_cs4: hsspi_cs4-pins {
0098 function = "hsspi_cs4";
0099 pins = "gpio16";
0100 };
0101
0102 pinctrl_hsspi_cs5: hsspi_cs5-pins {
0103 function = "hsspi_cs5";
0104 pins = "gpio17";
0105 };
0106
0107 pinctrl_hsspi_cs6: hsspi_cs6-pins {
0108 function = "hsspi_cs6";
0109 pins = "gpio8";
0110 };
0111
0112 pinctrl_hsspi_cs7: hsspi_cs7-pins {
0113 function = "hsspi_cs7";
0114 pins = "gpio9";
0115 };
0116
0117 pinctrl_adsl_spi: adsl_spi-pins {
0118 pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
0119 function = "adsl_spi_miso";
0120 pins = "gpio18";
0121 };
0122
0123 pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
0124 function = "adsl_spi_mosi";
0125 pins = "gpio19";
0126 };
0127 };
0128
0129 pinctrl_vreq_clk: vreq_clk-pins {
0130 function = "vreq_clk";
0131 pins = "gpio22";
0132 };
0133
0134 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
0135 function = "pcie_clkreq_b";
0136 pins = "gpio23";
0137 };
0138
0139 pinctrl_robosw_led_clk: robosw_led_clk-pins {
0140 function = "robosw_led_clk";
0141 pins = "gpio30";
0142 };
0143
0144 pinctrl_robosw_led_data: robosw_led_data-pins {
0145 function = "robosw_led_data";
0146 pins = "gpio31";
0147 };
0148
0149 pinctrl_nand: nand-pins {
0150 function = "nand";
0151 group = "nand_grp";
0152 };
0153
0154 pinctrl_gpio35_alt: gpio35_alt-pins {
0155 function = "gpio35_alt";
0156 pin = "gpio35";
0157 };
0158
0159 pinctrl_dectpd: dectpd-pins {
0160 function = "dectpd";
0161 group = "dectpd_grp";
0162 };
0163
0164 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
0165 function = "vdsl_phy_override_0";
0166 group = "vdsl_phy_override_0_grp";
0167 };
0168
0169 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
0170 function = "vdsl_phy_override_1";
0171 group = "vdsl_phy_override_1_grp";
0172 };
0173
0174 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
0175 function = "vdsl_phy_override_2";
0176 group = "vdsl_phy_override_2_grp";
0177 };
0178
0179 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
0180 function = "vdsl_phy_override_3";
0181 group = "vdsl_phy_override_3_grp";
0182 };
0183
0184 pinctrl_dsl_gpio8: dsl_gpio8-pins {
0185 function = "dsl_gpio8";
0186 group = "dsl_gpio8";
0187 };
0188
0189 pinctrl_dsl_gpio9: dsl_gpio9-pins {
0190 function = "dsl_gpio9";
0191 group = "dsl_gpio9";
0192 };
0193 };
0194 };
